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| Keyword : hardware
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Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A
No. 12 ;
pp. 2628-2638
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
block cipher, KASUMI, hardware, ASIC, FPGA, compact implementation, | | | Summary | Full Text:PDF | |
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A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders
Jui-Hui HUNG Sau-Gee CHEN | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A
No. 11 ;
pp. 2246-2253
Type of Manuscript:
Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Communication Theory and Signals
Keyword:
channel coding, LDPC decoder, comparison operation, algorithm, hardware, | | | Summary | Full Text:PDF | |
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An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
Jui-Hui HUNG Sau-Gee CHEN | Publication: IEICE TRANSACTIONS on Communications
Publication Date: 2010/11/01
Vol. E93-B
No. 11 ;
pp. 2980-2989
Type of Manuscript:
PAPER
Category: Fundamental Theories for Communications
Keyword:
channel coding, LDPC, decoder, algorithm, hardware, | | | Summary | Full Text:PDF | |
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Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
Dai YAMAMOTO Jun YAJIMA Kouichi ITOH | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A
No. 1 ;
pp. 3-12
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Symmetric Cryptography
Keyword:
block cipher, MISTY1, hardware, ASIC, compact implementation, | | | Summary | Full Text:PDF | |
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Security Evaluations of MRSL and DRSL Considering Signal Delays
Minoru SAEKI Daisuke SUZUKI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A
No. 1 ;
pp. 176-183
Type of Manuscript:
Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword:
DPA, data masking, dual-rail circuit, countermeasure, hardware, RSL, MRSL, DRSL, | | | Summary | Full Text:PDF | |
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