Keyword : hardware


Lightweight Security Hardware Architecture Using DWT and AES Algorithms
Ignacio ALGREDO-BADILLO Francisco R. CASTILLO-SORIA Kelsey A. RAMÍREZ-GUTIÉRREZ Luis MORALES-ROSALES Alejandro MEDINA-SANTIAGO Claudia FEREGRINO-URIBE 
Publication:   
Publication Date: 2018/11/01
Vol. E101-D  No. 11 ; pp. 2754-2761
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
hardwaresteganographycryptographyDWTFPGA
 Summary | Full Text:PDF(1.4MB)

Off-Chip Training with Additive Perturbation for FPGA-Based Hand Sign Recognition System
Hiroomi HIKAWA Masayuki TAMAKI Hidetaka ITO 
Publication:   
Publication Date: 2018/02/01
Vol. E101-A  No. 2 ; pp. 499-506
Type of Manuscript:  PAPER
Category: Neural Networks and Bioengineering
Keyword: 
hand sign recognitionself-organizing maphardwareoff-chip learningperturbation
 Summary | Full Text:PDF(2.7MB)

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher
Dai YAMAMOTO Kouichi ITOH Jun YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2628-2638
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
block cipherKASUMIhardwareASICFPGAcompact implementation
 Summary | Full Text:PDF(945.4KB)

A Fast Systematic Optimized Comparison Algorithm for CNU Design of LDPC Decoders
Jui-Hui HUNG Sau-Gee CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2246-2253
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Communication Theory and Signals
Keyword: 
channel codingLDPC decodercomparison operationalgorithmhardware
 Summary | Full Text:PDF(767.7KB)

An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
Jui-Hui HUNG Sau-Gee CHEN 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2010/11/01
Vol. E93-B  No. 11 ; pp. 2980-2989
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
channel codingLDPCdecoderalgorithmhardware
 Summary | Full Text:PDF(1008.4KB)

Compact Architecture for ASIC Implementation of the MISTY1 Block Cipher
Dai YAMAMOTO Jun YAJIMA Kouichi ITOH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A  No. 1 ; pp. 3-12
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Symmetric Cryptography
Keyword: 
block cipherMISTY1hardwareASICcompact implementation
 Summary | Full Text:PDF(599.3KB)

Efficient Memory Organization Framework for JPEG2000 Entropy Codec
Hiroki SUGANO Takahiko MASUZAKI Hiroshi TSUTSUI Takao ONOYE Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/08/01
Vol. E92-A  No. 8 ; pp. 1970-1977
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: Realization
Keyword: 
JPEG2000entropy codechardwarememory organization
 Summary | Full Text:PDF(600KB)

Hardware Neural Network for a Visual Inspection System
Seungwoo CHUN Yoshihiro HAYAKAWA Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 935-942
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
hardwarevisual inspection systemback-propagationPCI-BUSFPGA
 Summary | Full Text:PDF(935.2KB)

Security Evaluations of MRSL and DRSL Considering Signal Delays
Minoru SAEKI Daisuke SUZUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 176-183
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Side Channel Attacks
Keyword: 
DPAdata maskingdual-rail circuitcountermeasurehardwareRSLMRSLDRSL
 Summary | Full Text:PDF(352.5KB)

A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions
Mahdi MOTTAGHI-KASHTIBAN Abdollah KHOEI Khayrollah HADIDI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/06/01
Vol. E90-C  No. 6 ; pp. 1258-1266
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
fuzzy controllerTSKhardwarecurrent moderational-powered membership function
 Summary | Full Text:PDF(1.3MB)

A Real-Time Image Compressor Using 2-Dimensional DWT and Its FPGA Implementation
Young-Ho SEO Wang-Hyun KIM Ji-Sang YOO Dai-Gyoung KIM Dong-Wook KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/08/01
Vol. E87-A  No. 8 ; pp. 2110-2119
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
DWTwaveletcompressionFPGAdesignhardware
 Summary | Full Text:PDF(1.4MB)

Automatic Hardware Synthesis of Multimedia Synchronizers from High-Level Specifications
Kshirasagar NAIK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/06/25
Vol. E79-D  No. 6 ; pp. 743-751
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia Computing and Communications)
Category: 
Keyword: 
multimedia synchronizationtemporal relationswell-formed specificationtimed petri nethardware
 Summary | Full Text:PDF(816.7KB)

Design and Implementations of a Learning T-Model Neural Network
Zheng TANG Okihiko ISHIZUKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/02/25
Vol. E78-A  No. 2 ; pp. 259-263
Type of Manuscript:  LETTER
Category: Neural Networks
Keyword: 
neural networksHopfield modelT-Modellearningbackpropagationimplementationshardware
 Summary | Full Text:PDF(297.9KB)