Keyword : hardware design

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures
Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2020/07/01
Vol. E103-D  No. 7 ; pp. 1618-1622
Type of Manuscript:  Special Section LETTER (Special Section on Information and Communication System Security)
Category: Network and System Security
Keyword: 
hardware Trojan, gate-level netlist, Trojan feature, boundary nets, hardware design, 
 Summary | Full Text:PDF
Sorting Matrix Architecture for Continuous Data Sequences
Meiting XUE Huan ZHANG Weijun LI Feng YU 
Publication:   
Publication Date: 2020/02/01
Vol. E103-A  No. 2 ; pp. 542-546
Type of Manuscript:  LETTER
Category: Algorithms and Data Structures
Keyword: 
data sorting, variable-width, variable-length, hardware design, pipeline and parallel, 
 Summary | Full Text:PDF
Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description
Ignacio ALGREDO-BADILLO Claudia FEREGRINO-URIBE Rene CUMPLIDO Miguel MORALES-SANDOVAL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/10/01
Vol. E91-D  No. 10 ; pp. 2519-2523
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
MD5 algorithm, hardware design, FPGA implementation, hardware architectures, 
 Summary | Full Text:PDF
DMFQ: Hardware Design of Flow-Based Queue Management Scheme for Improving the Fairness
Norio YAMAGAKI Hideki TODE Koso MURAKAMI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2005/04/01
Vol. E88-B  No. 4 ; pp. 1413-1423
Type of Manuscript:  Special Section PAPER (Special Section on Internet Technology V)
Category: 
Keyword: 
Internet router, active queue management, fairness, hardware design, 
 Summary | Full Text:PDF