| Keyword : hardware architecture
| |
|
Full-HD 60fps FPGA Implementation of Spatio-Temporal Keypoint Extraction Based on Gradient Histogram and Parallelization of Keypoint Connectivity Takahiro SUZUKI Takeshi IKENAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/11/01
Vol. E99-A
No. 11 ;
pp. 1937-1946
Type of Manuscript:
Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Vision Keyword: hardware architecture, keypoint extraction, SIFT, cloud, video recognition, | | Summary | Full Text:PDF(3.3MB) | |
| |
| |
| |
| |
| |
| |
| |
|
A Performance Optimized Architecture of Deblocking Filter in H.264/AVC Kyeong-Yuk MIN Jong-Wha CHONG | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A
No. 4 ;
pp. 1038-1043
Type of Manuscript:
Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: Keyword: deblocking filter, hardware architecture, H.264, | | Summary | Full Text:PDF(1.6MB) | |
| |
|
Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding Myung-Suk BYEON Yil-Mi SHIN Yong-Beom CHO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A
No. 6 ;
pp. 1744-1745
Type of Manuscript:
Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: Keyword: H.264 encoding, image compression, motion estimation, hardware architecture, | | Summary | Full Text:PDF(148.6KB) | |
| |
| |
| |
| |
| |
|
|