IEICE Trans

Keyword : hardware architecture

SLIT: An Energy-Efficient Reconfigurable Hardware Architecture for Deep Convolutional Neural Networks Thi Diem TRAN Yasuhiko NAKASHIMA
Publication: Publication Date: 2021/07/01 Vol. E104-C No. 7 ; pp. 319-329 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: primary visual cortex, image classification, convolutional neural network, hardware architecture, FPGA, feature extraction,
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Full-HD 60fps FPGA Implementation of Spatio-Temporal Keypoint Extraction Based on Gradient Histogram and Parallelization of Keypoint Connectivity Takahiro SUZUKI Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/11/01 Vol. E99-A No. 11 ; pp. 1937-1946 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Vision Keyword: hardware architecture, keypoint extraction, SIFT, cloud, video recognition,
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Scalable Hardware Winner-Take-All Neural Network with DPLL Masaki AZUMA Hiroomi HIKAWA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/10/01 Vol. E98-D No. 10 ; pp. 1838-1846 Type of Manuscript: PAPER Category: Biocybernetics, Neurocomputing Keyword: neural network, winner-take-all, supervised learning, digital phase-locked loop, hardware architecture,
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Hardware Architecture of the Fast Mode Decision Algorithm for H.265/HEVC Wenjun ZHAO Takao ONOYE Tian SONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/08/01 Vol. E98-A No. 8 ; pp. 1787-1795 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: fast mode decision, H.265/HEVC, hardware architecture, mode dispatch module,
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Energy-Efficient IDCT Design for DS-CDMA Watermarking Systems Shan-Chun KUO Hong-Yuan JHENG Fan-Chieh CHENG Shanq-Jang RUAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/05/01 Vol. E96-A No. 5 ; pp. 995-996 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: DS-CDMA, watermarking, low-power system, hardware architecture,
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Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k4k@60 fps Yiqing HUANG Xiaocong JIN Jin ZHOU Jia SU Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 428-438 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264/AVC, intra prediction, hardware architecture, super hi-vision,
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A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder Gang HE Dajiang ZHOU Jinjia ZHOU Tianruo ZHANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 419-427 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264/AVC, intra prediction, data dependency, hardware architecture,
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How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 ; pp. 200-210 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, differential power analysis, correlation power analysis, template attack,
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How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation Daisuke SUZUKI Tsutomu MATSUMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 ; pp. 211-222 Type of Manuscript: Special Section PAPER (Special Section on Cryptography and Information Security) Category: Implementation Keyword: hardware architecture, modular exponentiation, Montgomery multiplication, FPGA, DSP,
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A Performance Optimized Architecture of Deblocking Filter in H.264/AVC Kyeong-Yuk MIN Jong-Wha CHONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 ; pp. 1038-1043 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: deblocking filter, hardware architecture, H.264,
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Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC Yiqing HUANG Zhenyu LIU Yang SONG Satoshi GOTO Takeshi IKENAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 ; pp. 987-997 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: H.264/AVC, variable block size motion estimation, hardware architecture,
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Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding Myung-Suk BYEON Yil-Mi SHIN Yong-Beom CHO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/06/01 Vol. E89-A No. 6 ; pp. 1744-1745 Type of Manuscript: Special Section LETTER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005)) Category: Keyword: H.264 encoding, image compression, motion estimation, hardware architecture,
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Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation Hakaru TAMUKOH Keiichi HORIO Takeshi YAMAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 ; pp. 1787-1794 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: self-organizing map, fast learning algorithm, rough comparison winner-take-all, hardware architecture,
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Adaptive Tessellation of PN Triangles Using Minimum-Artifact Edge Linking Yun-Seok CHOI Kyu-Sik CHUNG Lee-Sup KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/10/01 Vol. E87-A No. 10 ; pp. 2821-2828 Type of Manuscript: LETTER Category: Computer Graphics Keyword: 3D graphics, adaptive tessellation, PN triangle, edge linking, hardware architecture,
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Reduction of Background Computations in Block-Matching Motion Estimation Vasily G. MOSHNYAGA Koichi MASUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/03/01 Vol. E87-A No. 3 ; pp. 539-546 Type of Manuscript: Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing) Category: Video/Image Coding Keyword: motion estimation, video coding, computational complexity, hardware architecture, adaptive processing,
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Motion Estimation and Compensation Hardware Architecture for a Scene-Adaptive Algorithm on a Single-Chip MPEG-2 Video Encoder Koyo NITTA Toshihiro MINAMI Toshio KONDO Takeshi OGURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/03/01 Vol. E84-D No. 3 ; pp. 317-325 Type of Manuscript: PAPER Category: VLSI Systems Keyword: motion estimation and compensation, scene-adaptive algorithm, MPEG-2 video encoder, hardware architecture, SIMD,
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Parallel Move Generation System for Computer Chess Yi-Fan KE Tai-Ming PARNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/04/25 Vol. E79-D No. 4 ; pp. 290-296 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: computer chess, hardware architecture, parallel algorithm,
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