Keyword : global routing

Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing
Peng-Yang HUNG Ying-Shu LOU Yih-Lang LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/03/01
Vol. E92-A  No. 3 ; pp. 880-889
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
track routing, shield insertion, detailed routing, crosstalk optimization, global routing, VLSI layout optimization, 
 Summary | Full Text:PDF
Timing-Driven Global Routing with Efficient Buffer Insertion
Jingyu XU Xianlong HONG Tong JING 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 3188-3195
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI layout, global routing, timing-driven, buffer insertion, routability, 
 Summary | Full Text:PDF
Timing-Constrained Flexibility-Driven Routing Tree Construction
Jin-Tai YAN Yen-Hsiang CHEN Chia-Fang LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1360-1368
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
global routing, routing flexibility, Steiner tree, timing constraint, 
 Summary | Full Text:PDF
A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design
Jingyu XU Xianlong HONG Tong JING Yici CAI Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3158-3167
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Place and Routing
Keyword: 
high performance design, global routing, timing-driven, coupling effects, 
 Summary | Full Text:PDF
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layout, global routing, pin assignment, timing constraint, simulated evolution, 
 Summary | Full Text:PDF
An Efficient Timing-Driven Global Routing Method for Standard Cell Layout
Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1410-1418
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
standard cell layout, global routing, timing constraints, slack distribution, 0-1 integer linear programming, 
 Summary | Full Text:PDF
A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 345-352
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
branch-and-bound, layout, global routing, channel-intersection graph, analog, LSI, CAD, 
 Summary | Full Text:PDF
A Hybrid Hierarchical Global Router for Multi-Layer VLSI's
Masayuki HAYASHI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 337-344
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
hybrid hierarchical router, global routing, multi-layer routing, CAD, VLSI, 
 Summary | Full Text:PDF
A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
Ikuo HARADA Yuichiro TAKEI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2058-2066
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routing, timing driven layout, bipolar LSI, delay model, routing graph, critical path, 
 Summary | Full Text:PDF
Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGA, look up table, technology mapping, layout design, placement, global routing, 
 Summary | Full Text:PDF
A Layout System for Mixed A/D Standard Cell LSI's
Ikuo HARADA Hitoshi KITAZAWA Takao KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/25
Vol. E75-C  No. 3 ; pp. 322-332
Type of Manuscript:  Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
analog layout, floorplan, placement, global routing, channel routing, crossovers, crosstalk noise, 
 Summary | Full Text:PDF