Keyword : glitch

Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications
In-Young CHUNG Youngsoo SOHN Wonki PARK Changhyun KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 753-759
Type of Manuscript:  PAPER
Category: Electronic Circuits
DLLjittercounterhysteresiscompensationpower noiseglitch
 Summary | Full Text:PDF

Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1 ; pp. 234-240
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
low powerglitchgate sizingbuffer insertion
 Summary | Full Text:PDF