Keyword : general-synchronous framework


Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework
Junki KAWAGUCHI Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1366-1373
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
general-synchronous frameworktechnology mappinginteger linear programming
 Summary | Full Text:PDF(753.4KB)

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2459-2466
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
general-synchronous frameworkmulti-domain clock skew schedulingtwo-domain clock skew scheduling2-SAT
 Summary | Full Text:PDF(430.7KB)

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Yukihide KOHIRA Shuhei TANI Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1106-1114
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
delay insertionclock schedulinggeneral-synchronous framework
 Summary | Full Text:PDF(835.2KB)

A Fast Clock Scheduling for Peak Power Reduction in LSI
Yosuke TAKAHASHI Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3803-3811
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock schedulinggeneral-synchronous frameworkpeak power reductionpeak power wave estimation
 Summary | Full Text:PDF(825.6KB)

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10 ; pp. 3030-3037
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
register relocationretimingclock schedulinggeneral-synchronous framework
 Summary | Full Text:PDF(440.8KB)