Keyword : gate-level


Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 518-527
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
self synchronousgate-levelrobustnesssingle event upsetlow voltagereliability
 Summary | Full Text:PDF(6.1MB)

Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 546-554
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
power gatinggate-levelpipelineself synchronousenergy minimum operationFPGA
 Summary | Full Text:PDF(4.2MB)

Dynamic Supply Current Waveform Estimation with Standard Library Information
Mu-Shun Matt LEE Chien-Nan Jimmy LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/03/01
Vol. E93-A  No. 3 ; pp. 595-606
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dynamic supply currentgate-levelstandard library
 Summary | Full Text:PDF(639.9KB)

Pre-Route Power Analysis Techniques for SoC
Takashi YAMADA Takeshi SAKAMOTO Shinji FURUICHI Mamoru MUKUNO Yoshifumi MATSUSHITA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/03/01
Vol. E86-A  No. 3 ; pp. 686-692
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SoCpower analysisgate-levelcustom wire load model
 Summary | Full Text:PDF(763.6KB)