Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-CNo. 4 ;
pp. 518-527 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: self synchronous, gate-level, robustness, single event upset, low voltage, reliability,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-CNo. 4 ;
pp. 546-554 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: power gating, gate-level, pipeline, self synchronous, energy minimum operation, FPGA,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/03/01 Vol. E93-ANo. 3 ;
pp. 595-606 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dynamic supply current, gate-level, standard library,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/03/01 Vol. E86-ANo. 3 ;
pp. 686-692 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: SoC, power analysis, gate-level, custom wire load model,