Keyword : gate-grounded NMOS (ggNMOS)


Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process
Guangyi LU Yuan WANG Xing ZHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/05/01
Vol. E99-C  No. 5 ; pp. 590-596
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
electrostatic discharge (ESD)gate-grounded NMOS (ggNMOS)substrate-pickup stripestransmission-line-pulsing (TLP) test
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