Keyword : gate sizing


Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3251-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosstalk noisecapacitive coupling noisetransistor sizinggate sizingpost-layout optimization
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Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1 ; pp. 234-240
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerglitchgate sizingbuffer insertion
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Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizinglow power designcell-base designpost-layout optimizationgate sizing
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LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption
Yutaka TAMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 331-336
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
gate sizingtiming optimizationpower consumptionlinear programming
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Experiments with Power Optimization in Gate Sizing
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1913-1916
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
low power designpower dissipationgate sizingarea–power–delay tradeoff
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