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| Keyword : gate sizing
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Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A
No. 1 ;
pp. 234-240
Type of Manuscript:
PAPER
Category: VLSI Design Technology and CAD
Keyword:
low power, glitch, gate sizing, buffer insertion, | | | Summary | Full Text:PDF | |
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LP Based Cell Selection with Constraints of Timing, Area, and Power Consumption
Yutaka TAMIYA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A
No. 3 ;
pp. 331-336
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword:
gate sizing, timing optimization, power consumption, linear programming, | | | Summary | Full Text:PDF | |
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