Keyword : gate level partitioning

A Waveform Relaxation Method Applicable to the Simulation of ECL Circuits with Gate Level Partitioning
Vijaya Gopal BANDI Hideki ASAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/04/25
Vol. E76-A  No. 4 ; pp. 657-660
Type of Manuscript:  LETTER
Category: Neural Networks
circuit simulationgate level partitioningwaveform relaxationtransmission lines
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