Keyword : gate delay model

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low power, leakage, gate delay model, variation, 
 Summary | Full Text:PDF
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 990-997
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SSTA, output, transition time, gate delay model, process variation, 
 Summary | Full Text:PDF
Timing Analysis Considering Spatial Power/Ground Level Variation
Masanori HASHIMOTO Junji YAMAGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2661-2668
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
timing analysis, power supply noise, gate delay model, power/ground level variation, 
 Summary | Full Text:PDF