Keyword : gate delay fault


A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11 ; pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
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