Keyword : functional decomposition


A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix
Tsutomu SASAO Yuta URANO Yukihiro IGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2427-2433
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
minimal coverlinear transformationfunctional decompositionincompletely specified functionlogic minimization
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BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
Munehiro MATSUURA Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2762-2769
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword: 
incompletely specified functioncharacteristic functionbinary decision diagramfunctional decompositionLUT cascade
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Design Methods of Radix Converters Using Arithmetic Decompositions
Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/06/01
Vol. E90-D  No. 6 ; pp. 905-914
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
radix converterLUT cascadesFPGAfunctional decomposition
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A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3471-3481
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
LUT cascadebdd_for_cffunctional decomposition
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A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3342-3350
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
reconfigurable architectureLUT cascadeBDD_for_CFfunctional decomposition
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An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs
Yusuke MATSUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2715-2724
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionBDDslogic synthesisFPGA
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A General Framework to Use Various Decomposition Methods for LUT Network Synthesis
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2915-2922
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
functional decompositionalgebraic decompositionfield programmable gate array (FPGA)look-up table (LUT)
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Functional Decomposition with Application to LUT-Based FPGA Synthesis
Jian QIAO Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 2004-2013
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic synthesisfunctional decompositioncompatibility class encodingLUT-based FPGAs
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An Efficient Method for Finding an Optimal Bi-Decomposition
Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2529-2537
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
functional decompositionbi-decompositionANDXORlook-up table
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Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution
Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10 ; pp. 1017-1023
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
FPGAlook-up table (LUT)functional decompositionBoolean resubstitutionsupport minimization
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Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis
Kuo-Hua WANG Ting-Ting HWANG Cheng CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 1075-1084
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
communication complexityfunctional decompositionoverlapped decompositionglobalsDecomposition Don't Cares (DDC).
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