Keyword : four-phase dual-rail encoding


Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Shota ISHIHARA Ryoto TSUCHIYA Yoshiya KOMATSU Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/10/01
Vol. E94-C  No. 10 ; pp. 1669-1679
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
mixed synchronous/asynchronous designreconfigurable VLSIfour-phase dual-rail encodingself-timed architectureGALS (Globally Asynchronous Locally Synchronous)
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