Keyword : floorplanning


Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips
Wei ZHONG Song CHEN Bo HUANG Takeshi YOSHIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6 ; pp. 1174-1184
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
networks on chip (NoC)topology synthesisfloorplanning
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Floorplanning for High Utilization of Heterogeneous FPGAs
Nan LIU Song CHEN Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/09/01
Vol. E95-A  No. 9 ; pp. 1529-1537
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
field programmable gate arrayfloorplanninghigh utilization
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Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 506-515
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuitsbehavioral synthesisfloorplanning
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An Enhanced BSA for Floorplanning
Jyh Perng FANG Yang-Shan TONG Sao Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 528-534
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
floorplanningbuffer insertionroutingdominant wide bus
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A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanningtiming-driven layoutbuffer insertionwire sizingsimulated annealing
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Internet-Based Hierarchical Floorplan Design
Jiann-Horng LIN Jing-Yang JOU Iris Hui-Ru JIANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2414-2423
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
internetfloorplanning
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A Floorplanning Method with Topological Constraint Manipulation in VLSI Building Block Layout
Tetsushi KOIDE Yoshinori KATSURA Katsumi YAMATANI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2053-2057
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
building block layoutfloorplanningrelative placementtopological constraintstrong respecttentative insertionblock reshaping
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A Mathematical Formulation of Allocation and Floorplanning Problem in VLSI Data Path Synthesis
Shoichiro YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6 ; pp. 1043-1049
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
high-level synthesisdata path allocationfloorplanningmixed integer linear programming
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