IEICE Trans

Keyword : floorplan

A Design Method for Designing Asynchronous Circuits on Commercial FPGAs Using Placement Constraints Tatsuki OTAKE Hiroshi SAITO
Publication: Publication Date: 2020/12/01 Vol. E103-A No. 12 ; pp. 1427-1436 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: asynchronous circuits, FPGAs, placement constraints, floorplan,
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Enumerating Floorplans with Columns Katsuhisa YAMANAKA Md. Saidur RAHMAN Shin-ichi NAKANO
Publication: Publication Date: 2018/09/01 Vol. E101-A No. 9 ; pp. 1392-1397 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: enumeration, floorplan, algorithm,
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A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2911-2924 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: high-level synthesis, multiple-bitwidth, distributed-register architecture, operation chaining, interconnection delay, floorplan,
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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: Publication Date: 2017/07/01 Vol. E100-A No. 7 ; pp. 1439-1451 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, delay variation, body biasing, interconnection delay, floorplan,
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Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1294-1310 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: interconnection delay, clock skew, high-level synthesis (HLS), FPGA, floorplan,
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Uniformly Random Generation of Floorplans Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/03/01 Vol. E99-D No. 3 ; pp. 624-629 Type of Manuscript: Special Section PAPER (Special Section on Foundations of Computer Science---Developments of the Theory of Algorithms and Computation---) Category: Keyword: random generation, algorithm, floorplan, mosaic floorplan, classification tree,
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A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, RDR architecture, interconnection delay, operation chaining, floorplan,
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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/07/01 Vol. E98-A No. 7 ; pp. 1392-1405 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis (HLS), FPGA, floorplan, interconnection delay, MUX,
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Another Optimal Binary Representation of Mosaic Floorplans Katsuhisa YAMANAKA Shin-ichi NAKANO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/06/01 Vol. E98-A No. 6 ; pp. 1223-1224 Type of Manuscript: Special Section LETTER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: algorithm, coding, decoding, floorplan, mosaic floorplan,
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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3169-3179 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, floorplan, distributed-register architecture, generalized distributed-register architecture, local register, local controller,
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Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3103-3110 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: placement, floorplan, buffer insertion, module resizing, geometric programming,
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Counting Rectangular Drawings or Floorplans in Polynomial Time Youhei INOUE Toshihiko TAKAHASHI Ryo FUJIMAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 1115-1120 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: rectangular drawing, floorplan, enumerative combinatorics, dynamic programming,
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Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan Xiaoyi WANG Jin SHI Yici CAI Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3443-3450 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power/ground network, floorplan, IR drop,
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Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation Toshihiko TAKAHASHI Ryo FUJIMAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/04/01 Vol. E91-A No. 4 ; pp. 1071-1076 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: floorplan, representation, permutation, constraint graph,
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A Surjective Mapping from Permutations to Room-to-Room Floorplans Ryo FUJIMAKI Toshihiko TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 ; pp. 823-828 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: floorplan, representation, permutation, room-to-room,
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A Graph Based Soft Module Handling in Floorplan Hiroaki ITOGA Chikaaki KODAMA Kunihiro FUJIYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3390-3397 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan and Placement Keyword: floorplan, soft module, compaction graph, slack,
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Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge Chikaaki KODAMA Kunihiro FUJIYOSHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 ; pp. 1389-1396 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Programmable Logic, VLSI, CAD and Layout Keyword: empty room, dissection line, rectangular dissection, floorplan, module placement,
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EQ-Sequences for Coding Floorplans Hua-An ZHAO Chen LIU Yoji KAJITANI Keishi SAKANUSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3233-3243 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan Keyword: floorplan, placement, VLSI CAD, Q-sequence,
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Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints Makoto SUGIHARA Kazuaki MURAKAMI Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3174-3184 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: core-based design, SOC, TAM, test architecture, floorplan, test scheduling,
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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing Sheqin DONG Xianlong HONG Song CHEN Xin QI Ruijie WANG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3136-3147 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: floorplan, placement, solution space smoothing,
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Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2795-2798 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: low power design, wire length, floorplan, bit slice, one-hot code,
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An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy Chikaaki KODAMA Kunihiro FUJIYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 ; pp. 2785-2794 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: packing, floorplan, sequence-pair, Q-sequence,
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Recognition of Floorplan by Parametric BSG for Reuse of Layout Design Keishi SAKANUSHI Zhonglin WU Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 ; pp. 872-879 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: parametric BSG, layout, reuse, floorplan, technology migration,
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VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation Yuchun MA Xianlong HONG Sheqin DONG Yici CAI Chung-Kuan CHENG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 ; pp. 2697-2704 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Layout Keyword: floorplan, corner block list, simulated annealing, boundary constraints,
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A Pin Assignment and Global Routing Algorithm for Floorplanning Takahiro SHIOHARA Masahiro FUKUI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/08/25 Vol. E81-A No. 8 ; pp. 1725-1732 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: floorplan, pin assignment, global route, maximum flow algorithm,
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Air-Pressure Model and Fast Algorithms for Zero-Wasted-Area Layout of General Floorplan Tomonori IZUMI Atsushi TAKAHASHI Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-A No. 5 ; pp. 857-865 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: floorplan, layout, area optimization, air-pressure, zero-wasted-area,
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Rectilinear Shape Formation Method on Block Placement Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 ; pp. 446-454 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: floorplan, rectilinear, soft block, placement,
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A Layout System for Mixed A/D Standard Cell LSI's Ikuo HARADA Hitoshi KITAZAWA Takao KANEKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/03/25 Vol. E75-C No. 3 ; pp. 322-332 Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology) Category: Keyword: analog layout, floorplan, placement, global routing, channel routing, crossovers, crosstalk noise,
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