Keyword : floating-gate MOS transistor


Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1662-1668
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Non-Binary Architectures
Keyword: 
pass-transistor networkfloating-gate MOS transistorlogic-in-memory structureManhattan distanceflash EEPROM technologyfour-valued full adder
 Summary | Full Text:PDF(1.6MB)

Design and Evaluation of a 4-Valued Universal-Literal CAM for Cellular Logic Image Processing
Takahiro HANYU Manabu ARAKAKI Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 948-955
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multiple-Valued Architectures
Keyword: 
logic value conversion (LVC)floating-gate MOS transistorthreshold operationsingle-transistor cellfully parallel template matching
 Summary | Full Text:PDF(570.7KB)