IEICE Trans

Keyword : flash memory

Low-Power Fast Partial Firmware Update Technique of On-Chip Flash Memory for Reliable Embedded IoT Microcontroller Jisu KWON Moon Gi SEOK Daejin PARK
Publication: Publication Date: 2021/06/01 Vol. E104-C No. 6 ; pp. 226-236 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: bootloader, flash memory, firmware update, function block, function map,
	Summary \| Full Text:PDF

Construction of Parallel Random I/O Codes Using Coset Coding with Hamming Codes Akira YAMAWAKI Hiroshi KAMABE Shan LU
Publication: Publication Date: 2018/12/01 Vol. E101-A No. 12 ; pp. 2125-2134 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding theory for storage Keyword: parallel random I/O code, coset coding, flash memory,
	Summary \| Full Text:PDF

Worst-Case Performance of ILIFC with Inversion Cells Akira YAMAWAKI Hiroshi KAMABE Shan LU
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2662-2670 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory for Strage Keyword: flash memory, block erasure, index-less indexed flash code,
	Summary \| Full Text:PDF

On Zero Error Capacity of Nearest Neighbor Error Channels with Multilevel Alphabet Takafumi NAKANO Tadashi WADAYAMA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2647-2653 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Channel Coding Keyword: zero error capacity, flash memory, perfect Lee codes,
	Summary \| Full Text:PDF

RRWL: Round Robin-Based Wear Leveling Using Block Erase Table for Flash Memory Seon Hwan KIM Ju Hee CHOI Jong Wook KWAK
Publication: Publication Date: 2017/05/01 Vol. E100-D No. 5 ; pp. 1124-1127 Type of Manuscript: LETTER Category: Software System Keyword: flash memory, wear leveling, hidden cold block problem, bit array table, block erase table,
	Summary \| Full Text:PDF

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping Dongchul PARK Biplob DEBNATH David H.C. DU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/06/01 Vol. E99-D No. 6 ; pp. 1502-1511 Type of Manuscript: PAPER Category: Computer System Keyword: FTL, flash translation layer, CFTL, SSD, flash memory,
	Summary \| Full Text:PDF

Flash Code Utilizing Binary-Indexed Slice Encoding and Resizable-Clusters Michael Joseph TAN Yuichi KAJI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/12/01 Vol. E96-A No. 12 ; pp. 2360-2367 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: flash code, flash memory, binary-indexed, resizable-cluster method,
	Summary \| Full Text:PDF

Bidirectional Limited-Magnitude Error Correction Codes for Flash Memories Myeongwoon JEON Jungwoo LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/07/01 Vol. E96-A No. 7 ; pp. 1602-1608 Type of Manuscript: PAPER Category: Coding Theory Keyword: flash memory, error correction codes, limited magnitude errors, bidirectional errors,
	Summary \| Full Text:PDF

Flash-Aware Page Management Policy of a Navigation-Specialized Mobile DBMS for an Incremental Map Update KyoungWook MIN JeongDan CHOI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/05/01 Vol. E96-D No. 5 ; pp. 1211-1214 Type of Manuscript: LETTER Category: Data Engineering, Web Information Systems Keyword: mobile DBMS, flash memory, database page management, mobile navigation, navigation map update,
	Summary \| Full Text:PDF

The Expected Write Deficiency of Index-Less Indexed Flash Codes Yuichi KAJI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2130-2138 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: flash code, flash memory, index-less indexed flash code, random walk,
	Summary \| Full Text:PDF

Comparative Analysis of Bandgap-Engineered Pillar Type Flash Memory with HfO₂ and S₃N₄ as Trapping Layer Sang-Youl LEE Seung-Dong YANG Jae-Sub OH Ho-Jin YUN Kwang-Seok JEONG Yu-Mi KIM Hi-Deok LEE Ga-Won LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 ; pp. 831-836 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: SOHOS, high-k, gate-all-around, program/erase speed, flash memory,
	Summary \| Full Text:PDF

Enhancing Endurance of Huge-Capacity Flash Storage Systems by Selectively Replacing Data Blocks Wei-Neng WANG Kai NI Jian-She MA Zong-Chao WANG Yi ZHAO Long-Fa PAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 ; pp. 558-564 Type of Manuscript: PAPER Category: Computer System Keyword: wear leveling, flash memory, selective replacement, huge-capacity storage systems,
	Summary \| Full Text:PDF

On Improving the Reliability and Performance of the YAFFS Flash File System Seungjae BAEK Heekwon PARK Jongmoo CHOI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/12/01 Vol. E94-D No. 12 ; pp. 2528-2532 Type of Manuscript: LETTER Category: Software System Keyword: flash memory, file system, mount speed, performance evaluation, garbage collection,
	Summary \| Full Text:PDF

Adaptive Interference Mitigation for Multilevel Flash Memory Devices Myeongwoon JEON Kyungchul KIM Sungkyu CHUNG Seungjae CHUNG Beomju SHIN Jungwoo LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/11/01 Vol. E94-A No. 11 ; pp. 2453-2457 Type of Manuscript: LETTER Category: Analog Signal Processing Keyword: flash memory, interference cancellation, interference mitigation, error correction,
	Summary \| Full Text:PDF

An Empirical Study of FTL Performance in Conjunction with File System Pursuing Data Integrity In Hwan DOH Myoung Sub SHIM Eunsam KIM Jongmoo CHOI Donghee LEE Sam H. NOH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/08/01 Vol. E93-D No. 8 ; pp. 2302-2305 Type of Manuscript: LETTER Category: Software System Keyword: Flash Translation Layer (FTL), flash memory, file system, metadata, non-volatile RAM, write cache,
	Summary \| Full Text:PDF

NVFAT: A FAT-Compatible File System with NVRAM Write Cache for Its Metadata In Hwan DOH Hyo J. LEE Young Je MOON Eunsam KIM Jongmoo CHOI Donghee LEE Sam H. NOH
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/05/01 Vol. E93-D No. 5 ; pp. 1137-1146 Type of Manuscript: PAPER Category: Software Systems Keyword: non-volatile RAM (NVRAM), flash memory, file system, metadata, flash translation layer (FTL),
	Summary \| Full Text:PDF

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices Seongjae CHO Jung Hoon LEE Yoon KIM Jang-Gn YUN Hyungcheol SHIN Byung-Gook PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 ; pp. 596-601 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Flash/Advanced Memory Keyword: NAND, flash memory, program inhibition, self-boosting, FinFET, device simulation,
	Summary \| Full Text:PDF

SONOS-Type Flash Memory with HfO₂ Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition Jae Sub OH Kwang Il CHOI Young Su KIM Min Ho KANG Myeong Ho SONG Sung Kyu LIM Dong Eun YOO Jeong Gyu PARK Hi Deok LEE Ga Won LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 ; pp. 590-595 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Flash/Advanced Memory Keyword: SONOS, SOHOS, flash memory, high-k, HfO₂, nonvolatile memory, Atomic Layer Deposition,
	Summary \| Full Text:PDF

A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers Shinya KAJIYAMA Masamichi FUJITO Hideo KASAI Makoto MIZUNO Takanori YAMAGUCHI Yutaka SHINAGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/10/01 Vol. E92-C No. 10 ; pp. 1258-1264 Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors) Category: Keyword: flash memory, microcontroller, dual-core, shared ROM, pipeline, sense amplifier,
	Summary \| Full Text:PDF

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array Yoon KIM Seongjae CHO Gil Sung LEE Il Han PARK Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/05/01 Vol. E92-C No. 5 ; pp. 653-658 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: NAND, flash memory, stacked NAND, vertical channel,
	Summary \| Full Text:PDF

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory Doo-Hyun KIM Il Han PARK Seongjae CHO Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/05/01 Vol. E92-C No. 5 ; pp. 659-663 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: SONOS, flash memory, nitride-based charge trap memory, retention, multi-bit, double gate,
	Summary \| Full Text:PDF

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs Hochul LEE Youngchang YOON Ickhyun SONG Hyungcheol SHIN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/05/01 Vol. E91-C No. 5 ; pp. 776-779 Type of Manuscript: Special Section LETTER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: random telegraph signal noise, FN stress, flash memory, MOSFET,
	Summary \| Full Text:PDF

A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model Shinya KAJIYAMA Ken'ichiro SONODA Kazuo OTSUGA Hideaki KURATA Kiyoshi ISHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 526-533 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: flash memory, AG-AND, modeling, constant-charge-injection programming, lucky electron model,
	Summary \| Full Text:PDF

A 126 mm² 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Kazuo OTSUGA Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI Hitoshi KUME Kazuki HOMMA Teruhiko ITO Yoshinori SAKAMOTO Masahiro SHIMIZU Yoshinori IKEDA Osamu TSUCHIYA Kazunori FURUSAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/11/01 Vol. E90-C No. 11 ; pp. 2146-2156 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: flash memory, multilevel, inversion-layer-bit-line, AG-AND,
	Summary \| Full Text:PDF

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories Kazuo OTSUGA Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 ; pp. 772-778 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: flash memory, AG-AND, multilevel technology, constant-charge-injection programming,
	Summary \| Full Text:PDF

A 130-nm CMOS 95-mm² 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput Hideaki KURATA Shunichi SAEKI Takashi KOBAYASHI Yoshitaka SASAGO Tsuyoshi ARIGANE Keiichi YOSHIDA Yoshinori TAKASE Takayuki YOSHITAKE Osamu TSUCHIYA Yoshinori IKEDA Shunichi NARUMI Michitaro KANAMITSU Kazuto IZAWA Kazunori FURUSAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/10/01 Vol. E89-C No. 10 ; pp. 1469-1479 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: flash memory, AG-AND, multilevel, high speed programming, CCIP,
	Summary \| Full Text:PDF

Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate Kuk-Hwan KIM Hyunjin LEE Yang-Kyu CHOI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/05/01 Vol. E89-C No. 5 ; pp. 578-584 Type of Manuscript: Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices) Category: Si Devices and Processes Keyword: MONOS, SONOS, Fowler-Nordheim tunneling, flash memory, asymmetric double gate, nonvolatile memory,
	Summary \| Full Text:PDF

Trends in High-Density Flash Memory Technologies Takashi KOBAYASHI Hideaki KURATA Katsutaka KIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/10/01 Vol. E87-C No. 10 ; pp. 1656-1663 Type of Manuscript: Special Section PAPER (Special Section on New Era of Nonvolatile Memories) Category: Flash Memory Keyword: flash memory, high density, AG-AND, multilevel, high-speed programming,
	Summary \| Full Text:PDF

Forward Bias Enhanced Channel Hot Electron Injection for Low-Level Programming Improvement in Multilevel Flash Memory Caleb Yu-Sheng CHO Ming-Jer CHEN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/07/01 Vol. E87-C No. 7 ; pp. 1204-1207 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: flash memory, multilevel, staircase programming,
	Summary \| Full Text:PDF

A Paired MOS Charge Pump for Low Voltage Operation Jin-Hyeok CHOI Seong-Ik CHO Mu-Hun PARK Young-Hee KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/05/01 Vol. E86-C No. 5 ; pp. 859-863 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: charge pump, flash memory, high-voltage generator, low-voltage operation,
	Summary \| Full Text:PDF

A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories Hongchin LIN Funian LIANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/02/01 Vol. E86-C No. 2 ; pp. 229-235 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: current-mode, multilevel identifying circuit, flash memory, sense amplifier, offset,
	Summary \| Full Text:PDF

An Effective Flash Memory Manager for Reliable Flash Memory Space Management Han-joon KIM Sang-goo LEE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/06/01 Vol. E85-D No. 6 ; pp. 950-964 Type of Manuscript: PAPER Category: Databases Keyword: flash memory, logging, cleaning algorithm, cycle leveling, data collection,
	Summary \| Full Text:PDF

Review of Device Technologies of Flash Memories Takahiro OHNAKADO Natsuo AJIKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/06/01 Vol. E84-C No. 6 ; pp. 724-733 Type of Manuscript: INVITED PAPER (Special Issue on Nonvolatile Memories) Category: Flash Memories Keyword: flash memory, non-volatile semiconductor memory, floating gate,
	Summary \| Full Text:PDF

Process Synthesis Using TCAD: A Mixed-Signal Case Study Michael SMAYLING John RODRIGUEZ Alister YOUNG Ichiro FUJII
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/25 Vol. E82-C No. 6 ; pp. 983-991 Type of Manuscript: INVITED PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: process integration, process recipes, components, mixed-signal process, flash memory, LDMOS, ESD circuit,
	Summary \| Full Text:PDF

A High Voltage Generator Using Charge Pump Circuit for Low Voltage Flash Memories Kyeng-Won MIN Shi-Ho KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/05/25 Vol. E82-C No. 5 ; pp. 781-784 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: high voltage generator, charge pump circuit, flash memory,
	Summary \| Full Text:PDF

New Write/Erase Operation Technology for Flash EEPROM Cells to lmprove the Read Disturb Characteristics Tetsuo ENDOH Hirohisa IIZUKA Riichirou SHIROTA Fujio MASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/10/25 Vol. E80-C No. 10 ; pp. 1317-1323 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: flash memory, read disturb characteristics, write/erase operation, stress leakage current,
	Summary \| Full Text:PDF

New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films Tetsuo ENDOH Kazuyosi SHIMIZU Hirohisa IIZUKA Fujio MASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/10/25 Vol. E80-C No. 10 ; pp. 1310-1316 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: thin oxide films, stress leakage current, flash memory, step tonneling,
	Summary \| Full Text:PDF

Tunnel Oxynitride Film Formation for Highly Reliable Flash Memory Tomiyuki ARAKAWA Ryoichi MATSUMOTO Takahisa HAYASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 819-824 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Nonvolatile memories Keyword: flash memory, oxynitride tunnel film, endurance, disturbance, retention,
	Summary \| Full Text:PDF

A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories Hiroshi NAKAMURA Jun-ichi MIYAMOTO Ken-ichi IMAMIYA Yoshihisa IWATA Yoshihisa SUGIURA Hideko OODAIRA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 836-844 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Nonvolatile memories Keyword: flash memory, sense amplifier, bit-by-bit program verify, capacitive coupling, page copy,
	Summary \| Full Text:PDF

2V/120 ns Embedded Flash EEPROM Circuit Technology Horoshige HIRANO Toshiyuki HONDA Shigeo CHAYA Takahiro FUKUMOTO Tatsumi SUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 825-831 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Nonvolatile memories Keyword: flash memory, low voltage operation, erase algorithm, boost circuit,
	Summary \| Full Text:PDF

A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices Toshihiko HIMENO Naohiro MATSUKAWA Hiroaki HAZAMA Koji SAKUI Masamitsu OSHIKIRI Kazunori MASUDA Kazushige KANDA Yasuo ITOH Jin-ichi MIYAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/02/25 Vol. E79-C No. 2 ; pp. 145-151 Type of Manuscript: Special Section PAPER (Special Issue on Microelectronic Test Structures) Category: Device and Circuit Characterization Keyword: flash memory, V_th distribution, reliability, NAND flash, nonvolatile memory,
	Summary \| Full Text:PDF

A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 ; pp. 818-824 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: flash memory, NAND, folded bit line verify read, charge pump,
	Summary \| Full Text:PDF

Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme Katsutaka KIMURA Toshihiro TANAKA Masataka KATO Tetsuo ADACHI Keisuke OGURA Hitoshi KUME
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 ; pp. 832-837 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: flash memory, program, erase, Fowler-Nordheim tunneling, sector,
	Summary \| Full Text:PDF

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme Hiroshi SUGAWARA Toshio TAKESHIMA Hiroshi TAKADA Yoshiaki S. HISAMUNE Kohji KANAMORI Takeshi OKAZAWA Tatsunori MUROTANI Isao SASAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/25 Vol. E78-C No. 7 ; pp. 825-831 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: flash memory, 64 Mbit, multi-bit programming, data register, hierarchical,
	Summary \| Full Text:PDF

A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories Kohji KANAMORI Yosiaki S. HISAMUNE Taishi KUBOTA Yoshiyuki SUZUKI Masaru TSUKIJI Eiji HASEGAWA Akihiko ISHITANI Takeshi OKAZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 ; pp. 1296-1302 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: Non-volatile Memory Keyword: F-N tunneling, flash memory, oxynitride, low power supply,
	Summary \| Full Text:PDF

Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories Hiroshi ONODA Yuichi KUNORI Kojiro YUZURIHA Shin-ichi KOBAYASHI Kiyohiko SAKAKIBARA Makoto OHI Atsushi FUKUMOTO Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 ; pp. 1279-1286 Type of Manuscript: Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: Non-volatile Memory Keyword: Fowler-Nordheim tunneling, virtual ground array, flash memory, NOR, asymmetrical source/drain structure,
	Summary \| Full Text:PDF

Sub-Halfmicron Flash Memory Technologies Koji SAKUI Fujio MASUOKA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/08/25 Vol. E77-C No. 8 ; pp. 1251-1259 Type of Manuscript: INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories) Category: Non-volatile Memory Keyword: magnetic memory, core memory, EEPROM, flash memory, NAND EEPROM,
	Summary \| Full Text:PDF

A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory Ken-ichi OYAMA Noriaki KODAMA Hiroki SHIRAI Kenji SAITOH Yosiaki S. HISAMUNE Takeshi OKAZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/11/25 Vol. E75-C No. 11 ; pp. 1358-1363 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Keyword: flash memory, 64 Mbit, DSA structure, erasing scheme, charge pumping,
	Summary \| Full Text:PDF