Keyword : fault tolerant processor arrays

An FPGA Implementation of a Self-Reconfigurable System for the 1 1/2 Track-Switch 2-D Mesh Array with PE Faults
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/08/25
Vol. E83-D  No. 8 ; pp. 1701-1705
Type of Manuscript:  LETTER
Category: Fault Tolerance
fault tolerant processor arrays1 1/2 track-switch modelself-reconfigurable systemrun-time fault tolerancewafer scale integration
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