Keyword : fault simulation


Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6 ; pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3506-3513
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
fault simulationtest generationstuck-open faultsstuck-at testsdefect coverage
 Summary | Full Text:PDF(283.9KB)

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information
Yuzo TAKAMATSU Hiroshi TAKAHASHI Yoshinobu HIGAMI Takashi AIKYO Koji YAMAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 675-682
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
diagnosisfault modelfault locationfault simulationcombinational circuitspass/fail information
 Summary | Full Text:PDF(491.4KB)

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools
Yoshinobu HIGAMI Kewal K. SALUJA Hiroshi TAKAHASHI Shin-ya KOBAYASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 690-699
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
transistor shortfault simulationtest generationstuck-at test tool
 Summary | Full Text:PDF(346.3KB)

Reduction of the Target Fault List and Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino Circuits
Kazuya SHIMIZU Takanori SHIRAI Masaya TAKAMURA Noriyoshi ITAZAKI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1526-1533
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
domino circuitcrosstalk faulttarget fault reductionfault simulation
 Summary | Full Text:PDF(155.9KB)

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
 Summary | Full Text:PDF(322.4KB)

Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation
Hiroshi TAKAHASHI Marong PHADOONGSIDHI Yoshinobu HIGAMI Kewal K. SALUJA Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1515-1525
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
diagnosiscrosstalk faultfault simulationsequential circuit
 Summary | Full Text:PDF(870.8KB)

Transistor Leakage Fault Diagnosis for CMOS Circuits
Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 697-705
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
fault diagnosistransistor leakage faultIDDQprimary outputfault simulationdiagnostic test generation
 Summary | Full Text:PDF(868.3KB)

Transistor Leakage Fault Diagnosis with IDDQ and Logic Information
Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4 ; pp. 372-381
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosistransistor leakage faultIDDQ testingfault simulationdiagnostic vector generation
 Summary | Full Text:PDF(985.7KB)

A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Noriyoshi ITAZAKI Yasutaka IDOMOTO Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 38-43
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Testing/Checking
Keyword: 
crosstalk faultfault simulationsequential circuittest
 Summary | Full Text:PDF(526.4KB)

Intelligent Trouble Management System Based on Operation Scenario and Fault Simulation
Kisaku FUJIMOTO Masakazu BABA Nobuaki SHIMIZU Masahiko MATSUSHITA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1995/01/25
Vol. E78-B  No. 1 ; pp. 31-38
Type of Manuscript:  Special Section PAPER (Special Issue on Network Operations and Management)
Category: 
Keyword: 
trouble managementdynamic scenario modificationfault simulationoperation systemservice/network managementmodel base reasoning
 Summary | Full Text:PDF(837.5KB)

An Efficient Fault Simulation Method for Reconvergent Fan-Out Stem
Sang Seol LEE Kyu Ho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 771-775
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault simulationreconvergent fan-out stemcombinational circuitprimary stem regionexit line
 Summary | Full Text:PDF(376KB)

Linear Time Fault Simulation Algorithm Using a Content Addressable Memory
Nagisa ISHIURA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/25
Vol. E75-A  No. 3 ; pp. 314-320
Type of Manuscript:  INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
fault simulationcontent addressable memoryparallel computation
 Summary | Full Text:PDF(539.6KB)