Keyword : fault coverage


Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion
Wenpo ZHANG Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/10/01
Vol. E97-D  No. 10 ; pp. 2719-2729
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
small-delay defectsfault coveragesegmented scancontrol pointobservation point
 Summary | Full Text:PDF(752KB)

A Low Power Test Pattern Generator for BIST
Shaochong LEI Feng LIANG Zeye LIU Xiaoying WANG Zhen WANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 696-702
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
built-in self-test (BIST)powersingle input change (SIC)fault coverage
 Summary | Full Text:PDF(1MB)

Effect of BIST Pretest on IC Defect Level
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/10/01
Vol. E89-D  No. 10 ; pp. 2626-2636
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(1.2MB)

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST
Yoshiyuki NAKAMURA Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/06/01
Vol. E88-D  No. 6 ; pp. 1210-1216
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault coveragedefect level
 Summary | Full Text:PDF(629.9KB)

Defect Level Prediction Using Multi-Model Fault Coverage
Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/06/01
Vol. E87-D  No. 6 ; pp. 1488-1495
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
defect levelfault coveragemulti-model fault coverageyield
 Summary | Full Text:PDF(455.5KB)

Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing
Kiyoshi FURUYA Susumu YAMAZAKI Masayuki SATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 889-894
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
built-in self-test (BIST)two-pattern testfault coveragetransition coverage
 Summary | Full Text:PDF(498.9KB)

The Effect of CMOS VLSI IDDq Measurement on Defect Level
Junichi HIRASE Masanori HAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 839-844
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
IDDq testCMOS VLSIfault coveragedefect leveltoggle ratestuck-at faultdesign for testability
 Summary | Full Text:PDF(409.2KB)