Keyword : failure analysis

A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis
Chizu MATSUMOTO Yuichi HAMAMURA Yoshiyuki TSUNODA Hiroshi UOZAKI Isao MIYAZAKI Shiro KAMOHARA Yoshiyuki KANEKO Kenji KANAMITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 353-360
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defects, failure analysis, fail bit signature, critical area analysis, integrated circuit layout, 
 Summary | Full Text:PDF
New Approach of Laser-SQUID Microscopy to LSI Failure Analysis
Kiyoshi NIKAWA Shouji INOUE Tatsuoki NAGAISHI Toru MATSUMOTO Katsuyoshi MIURA Koji NAKAMAE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/03/01
Vol. E92-C  No. 3 ; pp. 327-333
Type of Manuscript:  INVITED PAPER (Special Section on Recent Progress in Superconducting Analog Devices and Their Applications)
Category: 
Keyword: 
SQUID, laser, LSI chip, failure analysis, defect localization, 
 Summary | Full Text:PDF
Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor Manufacturing
Yuichi HAMAMURA Chizu MATSUMOTO Yoshiyuki TSUNODA Koji KAMODA Yoshio IWATA Kenji KANAMITSU Daisuke FUJIKI Fujihiko KOJIKA Hiromi FUJITA Yasuo NAKAGAWA Shun'ichi KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/01/01
Vol. E92-C  No. 1 ; pp. 144-152
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defects, failure analysis, yield estimation, integrated circuit layout, simulation, 
 Summary | Full Text:PDF
Fast Handover Failure-Case Analysis in Hierarchical Mobile IPv6 Networks
Dong SU Sang-Jo YOO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/06/01
Vol. E89-B  No. 6 ; pp. 1892-1895
Type of Manuscript:  LETTER
Category: Network
Keyword: 
fast handover, hierarchical, mobile IP, failure analysis, 
 Summary | Full Text:PDF
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11 ; pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verification, failure analysis, timed circuits, timing constraints, 
 Summary | Full Text:PDF
Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns
Takashi NASUNO Yoshihisa MATSUBARA Hiromasa KOBAYASHI Akiyuki MINAMI Eiichi SODA Hiroshi TSUDA Koichiro TSUJITA Wataru WAKAMIYA Nobuyoshi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 796-803
Type of Manuscript:  Special Section PAPER (Special Section on Microelectronic Test Structures)
Category: 
Keyword: 
test structure, 65 nm-node, via chain, OBIRCH, failure analysis, 
 Summary | Full Text:PDF
Laser-SQUID Microscopy as a Novel Tool for Inspection, Monitoring and Analysis of LSI-Chip-Defects: Nondestructive and Non-electrical-contact Technique
Kiyoshi NIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3 ; pp. 746-751
Type of Manuscript:  INVITED PAPER (Special Issue on Superconductive Electronics)
Category: Instruments and Coolers
Keyword: 
high Tc DC-SQUID, optical beam induced current, photo current, high spatial resolution, electrical defects, inspection, failure analysis, 
 Summary | Full Text:PDF
Highly Sensitive OBIRCH System for Fault Localization and Defect Detection
Kiyoshi NIKAWA Shoji INOUE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 743-748
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Beam Testing/Diagnosis
Keyword: 
VLSI chip, fault localization, metal line defect detection, high resistivity, TiSi, Al, reliability, yield, failure analysis, 
 Summary | Full Text:PDF
Observation Techinique for Process-Induced Defects Using Anodic Oxidation
Morio INOUE Shinji FUJII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 324-327
Type of Manuscript:  Special Section PAPER (Special Issue on Scientific ULSI Manufacturing Technology)
Category: Particle/Defect Control and Analysis
Keyword: 
delineation, defect, anodic oxidation, fabrication, failure analysis, 
 Summary | Full Text:PDF
Optical Beam Induced Current Technique as a Failure Analysis Tool of EPROMs
Jun SATOH Hiroshi NAMBA Tadashi KIKUCHI Kenichi YAMADA Hidetoshi YOSHIOKA Miki TANAKA Ken SHONO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4 ; pp. 574-578
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
data retention failure, EMS, EPROM, failure analysis, OBIC, 
 Summary | Full Text:PDF
An Analysis of and a Method of Enhancing the Intensity of OBIRCH Signal for Defects Observation in VLSI Metal Interconnections
Naoki KAWAMURA Tomoaki SAKAI Masakazu SHIMAYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4 ; pp. 579-584
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
OBIRCH, VLSI interconnection, failure analysis, defect observation, laser scanning microscope, OBIC, 
 Summary | Full Text:PDF