Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-ANo. 12 ;
pp. 2463-2471 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: memory BIST, BISR, embedded SRAM, area per good die, iterative improvement algorithm,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/03/01 Vol. E86-CNo. 3 ;
pp. 439-446 Type of Manuscript: Special Section PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02)) Category: Keyword: embedded SRAM, scaling merit, 3-dimensional interconnect simulation, 50 and 70 nm technology nodes,
Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme Koichi MORIKAWAJiro IDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-CNo. 12 ;
pp. 1713-1719 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: local wiring, junction capacitance, embedded SRAM, coupling noise,
