Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/05/01 Vol. E94-ANo. 5 ;
pp. 1201-1209 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: static timing analysis, gate delay, effective capacitance, non-iterative,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-ANo. 10 ;
pp. 2531-2539 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Problems Keyword: static timing analysis, gate delay, effective capacitance, Thevenin model,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-ANo. 12 ;
pp. 3367-3374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: static timing analysis, gate slew, CMOS inverter, effective capacitance, interconnect loads,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-ANo. 10 ;
pp. 2562-2569 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: static timing analysis, gate delay, CMOS inverter, effective capacitance, interconnect loads,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/08/01 Vol. E88-ANo. 8 ;
pp. 2206-2215 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: inductance criteria, effective capacitance, multi-ramp driver model, interconnect model,
Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design Norio OHKUBOTakeo YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-CNo. 4 ;
pp. 618-623 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: delay calculation, effective capacitance, logic circuit optimization, delay optimization, LSI design,