Keyword : dual-loop clock and data recovery (CDR)


A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 165-170
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
dual-loop clock and data recovery (CDR)phase interpolatorphase resolution
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