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A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
Rong-Jyi YANG Shen-Iuan LIU | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2005/08/01
Vol. E88-C
No. 8 ;
pp. 1726-1730
Type of Manuscript:
Special Section PAPER (Special Section on Papers Selected from AP-ASIC 2004)
Category:
Keyword:
DLL, CDR, dual loop, | | | Summary | Full Text:PDF | |
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