Keyword : double-gate


Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass
Akito HARA Shinya KAMO Tadashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/11/01
Vol. E97-C  No. 11 ; pp. 1048-1054
Type of Manuscript:  INVITED PAPER (Special Section on Electronic Displays)
Category: 
Keyword: 
poly-SiTFTdouble-gatefour-terminalsystem-on-glass
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Self-Aligned Planar Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate
Hiroyuki OGATA Kenji ICHIJO Kenji KONDO Akito HARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/02/01
Vol. E96-C  No. 2 ; pp. 285-288
Type of Manuscript:  BRIEF PAPER
Category: Semiconductor Materials and Devices
Keyword: 
poly-SiTFTdouble-gateglass substrate
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Technology Modeling for Emerging SOI Devices
Meikei IEONG Phil OLDIGES 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/03/01
Vol. E86-C  No. 3 ; pp. 301-307
Type of Manuscript:  INVITED PAPER (Special Issue on the 2002 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'02))
Category: 
Keyword: 
TCADdevice modelingsilicon-on-insulatorstrained-silicondouble-gate
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High-Speed and Low-Power n+-p+ Double-Gate SOI CMOS
Kunihiro SUZUKI Tetsu TANAKA Yoshiharu TOSAKA Hiroshi HORIE Toshihiro SUGII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 360-367
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Device Technology
Keyword: 
MOSFETSOIdouble-gatehigh-speedlow-powerthreshold voltage
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