IEICE Trans

Keyword : digital signal processor

Robust Voice Activity Detection Algorithm Based on Feature of Frequency Modulation of Harmonics and Its DSP Implementation Chung-Chien HSU Kah-Meng CHEONG Tai-Shih CHI Yu TSAO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/10/01 Vol. E98-D No. 10 ; pp. 1808-1817 Type of Manuscript: PAPER Category: Speech and Hearing Keyword: digital signal processor, frequency modulation, spectro-temporal analysis, voice activity detection,
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Active Noise Control System for Reducing MR Noise Masafumi KUMAMOTO Masahiro KIDA Ryotaro HIRAYAMA Yoshinobu KAJIKAWA Toru TANI Yoshimasa KURUMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/07/01 Vol. E94-A No. 7 ; pp. 1479-1486 Type of Manuscript: PAPER Category: Engineering Acoustics Keyword: active noise control, magnetic resonance imaging device, optical microphone, piezoelectric loudspeaker, digital signal processor,
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Fast Implementation Technique for Improving Throughput of RLS Adaptive Filters Kiyoshi NISHIKAWA Hitoshi KIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/08/25 Vol. E83-A No. 8 ; pp. 1545-1550 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Adaptive Signal Processing Keyword: adaptive system, pipeline processing, digital signal processor, RLS adaptive filters,
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Simulation of Series-Parallel Resonant DC-DC Converter System with DSP-Based Digital Control Scheme Ulhaqsyed MOBIN Eiji HIRAKI Hiroshi TAKANO Mutsuo NAKAOKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/07/25 Vol. E83-A No. 7 ; pp. 1458-1466 Type of Manuscript: PAPER Category: General Fundamentals and Boundaries Keyword: circuit simulation, digital signal processor, DC-DC power conversion, resonant power conversion, switched resistor circuit,
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Software Radio Base and Personal Station Prototypes Yasuo SUZUKI Kazuhiro UEHARA Masashi NAKATSUGAWA Yushi SHIRATO Shuji KUBOTA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2000/06/25 Vol. E83-B No. 6 ; pp. 1261-1268 Type of Manuscript: Special Section PAPER (Special Issue on Software Defined Radio and Its Technologies) Category: Keyword: software, software radio, digital signal processor, personal handy phone system,
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Performance Enhancement on Digital Signal Processors with Complex Arithmetic Capability Yoshimasa NEGISHI Eiji WATANABE Akinori NISHIHARA Takeshi YANAGISAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 ; pp. 238-245 Type of Manuscript: Special Section PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: digital signal processor, digital signal processing, complex signal processing, digital filter, complex multiplier,
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DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/12/25 Vol. E80-A No. 12 ; pp. 2562-2571 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: digital signal processor, compiler, code optimization, memory addressing,
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A Built-In Self-Test for ADC and DAC in a Single-Chip Speech CODEC Eiichi TERAOKA Toru KENGAKU Ikuo YASUI Kazuyuki ISHIKAWA Takahiro MATSUO Hideyuki WAKADA Narumi SAKASHITA Yukihiko SHIMAZU Takeshi TOKUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/25 Vol. E80-A No. 2 ; pp. 339-345 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration) Category: Keyword: built-in self-test, CODEC, digital signal processor,
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A 28 mW 16-bit Digital Signal Processor for the PDC Half-Rate CODEC Taketora SHIRAISI Koji KAWAMOTO Kazuyuki ISHIKAWA Eiichi TERAOKA Hidehiro TAKATA Takeshi TOKUDA Kouichi NISHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-C No. 12 ; pp. 1679-1685 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: digital signal processor, CODEC, low power consumption,
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A 16-bit Digital Signal Processor with Specially Arranged Multiply-Accumulator for Low Power Consumption Katsuhiko UEDA Toshio SUGIMURA Toshihiro ISHIKAWA Minoru OKAMOTO Mikio SAKAKIHARA Shinichi MARUI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/25 Vol. E78-C No. 12 ; pp. 1709-1716 Type of Manuscript: Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: integrated electronics, digital signal processor, low power consumption, communication,
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VIRGO: Hierarchical DSP Code Generator Based on Vectorized Signal Flow Graph Description Norichika KUMAMOTO Keiji AOKI Hiroaki KUNIEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/08/25 Vol. E75-A No. 8 ; pp. 1004-1013 Type of Manuscript: Special Section PAPER (Special Section on the 6th Digital Signal Processing Symposium) Category: Keyword: digital signal processor, code generation, hierarchical scheduling, vectorized-signal flow graph,
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