Keyword : digital signal processor (DSP)


Loop and Address Code Optimization for Digital Signal Processors
Jong-Yeol LEE In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6 ; pp. 1408-1415
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
digital signal processor (DSP)compilercode optimization
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Asynchronous Multirate Real-Time Scheduling for Programmable DSPs
Ichiro KURODA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1 ; pp. 241-247
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
digital signal processor (DSP)multirate signal processingasynchronousscheduling
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Area and Delay Estimation in Hardware/Software Cosynthesis for Digital Signal Processor Cores
Nozomu TOGAWA Yoshiharu KATAOKA Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2639-2647
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
area estimationdelay estimationhardware/software cosynthesisdigital signal processor (DSP)microprocessor
 Summary | Full Text:PDF

A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files
Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2802-2807
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
hardware/software cosynthesishardware/software partitioningdigital signal processor (DSP)register filehardware unit
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Memory Access Estimation of Filter Bank Implementation on Different DSP Architectures
Naoki MIZUTANI Shogo MURAMATSU Hisakazu KIKUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 1951-1959
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
digital signal processor (DSP)filter bankwavelet transformmultiplier and accumulator (MAC)
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