Keyword : digital phase-locked loop

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector
Zule XU Anugerah FIRDAUZI Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA 
Publication:   
Publication Date: 2019/07/01
Vol. E102-C  No. 7 ; pp. 520-529
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies)
Category: 
Keyword: 
type-I, digital phase-locked loop, ring-based PLL, 
 Summary | Full Text:PDF
Robust Phase Estimation of a Hybrid Monte Carlo/Finite Memory Digital Phase-Locked Loop
Sang-Su LEE Sung-Hyun YOU Seok-Kyoon KIM 
Publication:   
Publication Date: 2019/05/01
Vol. E102-D  No. 5 ; pp. 1089-1092
Type of Manuscript:  LETTER
Category: Data Engineering, Web Information Systems
Keyword: 
digital phase-locked loop, Monte Carlo estimation, finite memory estimation, hybrid estimation, 
 Summary | Full Text:PDF
Scalable Hardware Winner-Take-All Neural Network with DPLL
Masaki AZUMA Hiroomi HIKAWA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/10/01
Vol. E98-D  No. 10 ; pp. 1838-1846
Type of Manuscript:  PAPER
Category: Biocybernetics, Neurocomputing
Keyword: 
neural network, winner-take-all, supervised learning, digital phase-locked loop, hardware architecture, 
 Summary | Full Text:PDF