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Dual-Loop Digital PLL Design for Adaptive Clock Recovery Tae Hun KIM Beomsup KIM | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A
No. 12 ;
pp. 2509-2514
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Transistor-level Circuit Analysis, Design and Verification Keyword: digital PLL, DPLL, PLL, adaptive algorithm, clock recovery, | | Summary | Full Text:PDF | |
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