Keyword : digital PLL

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design
Zule XU Takayuki KAWAHARA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 370-372
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
ring oscillator, phase-locked loop, behavioral model, digital PLL, 
 Summary | Full Text:PDF
Method of Non-Data-Aided Carrier Recovery with Modulation Identification
Kenta UMEBAYASHI Robert H. MORELOS-ZARAGOZA Ryuji KOHNO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 656-665
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
software defined radio, carrier recovery, digital PLL, modulation identification, 
 Summary | Full Text:PDF
Design of Simplified Coherent QPSK Modem for Frequency Hopping Spread Spectrum
Satoru ISHII Atsushi HOSHIKUKI Ryuji KOHNO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/12/01
Vol. E84-A  No. 12 ; pp. 2966-2975
Type of Manuscript:  Special Section PAPER (Special Section on Spread Spectrum Techniques and Applications)
Category: 
Keyword: 
spread spectrum, symbol synchronization, coherent demodulation, carrier extraction, digital PLL, 
 Summary | Full Text:PDF
Dual-Loop Digital PLL Design for Adaptive Clock Recovery
Tae Hun KIM Beomsup KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2509-2514
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Transistor-level Circuit Analysis, Design and Verification
Keyword: 
digital PLL, DPLL, PLL, adaptive algorithm, clock recovery, 
 Summary | Full Text:PDF