Keyword : design-for-testability


A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
Fara ASHIKIN Masaki HASHIZUME Hiroyuki YOTSUYANAGI Shyue-Kung LU Zvi ROTH 
Publication:   
Publication Date: 2018/08/01
Vol. E101-D  No. 8 ; pp. 2053-2063
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
3D stacked ICopen defectsdesign-for-testabilitythrough-silicon viaelectrical interconnect test
 Summary | Full Text:PDF(934.9KB)

Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9 ; pp. 2232-2236
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(468.4KB)

Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/08/01
Vol. E99-D  No. 8 ; pp. 2182-2185
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(399.6KB)

Properties of Generalized Feedback Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4 ; pp. 1255-1258
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(395.2KB)

Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/10/01
Vol. E98-D  No. 10 ; pp. 1852-1855
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(352.9KB)

Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design
Katsuya FUJIWARA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5 ; pp. 1125-1133
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentsshift register quasi-equivalentsgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(1.7MB)

Hybrid Test Application in Partial Skewed-Load Scan Design
Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2571-2578
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay testingdesign-for-testabilityskewed-load test applicationbroad-side test applicationpartial skewed-load scan designhybrid test application
 Summary | Full Text:PDF(782.1KB)

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1430-1439
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentssecurityscan-based side-channel attack
 Summary | Full Text:PDF(599.1KB)

Embedded Memory Array Testing Using a Scannable Configuration
Seiken YANO Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1934-1944
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
scannable memory configurationmemory array testingdesign-for-testabilityscan design
 Summary | Full Text:PDF(823.2KB)

Application of Full Scan Design to Embedded Memory Arrays
Seiken YANO Katsutoshi AKAGI Hiroki INOHARA Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 514-520
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
design-for-testabilityDFT scan designscannable memory arraymemory array testing
 Summary | Full Text:PDF(621.8KB)