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Keyword : design-for-testability

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs Fara ASHIKIN Masaki HASHIZUME Hiroyuki YOTSUYANAGI Shyue-Kung LU Zvi ROTH
Publication: Publication Date: 2018/08/01 Vol. E101-D No. 8 ; pp. 2053-2063 Type of Manuscript: PAPER Category: Dependable Computing Keyword: 3D stacked IC, open defects, design-for-testability, through-silicon via, electrical interconnect test,
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Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents Hideo FUJIWARA Katsuya FUJIWARA
Publication: Publication Date: 2017/09/01 Vol. E100-D No. 9 ; pp. 2232-2236 Type of Manuscript: LETTER Category: Dependable Computing Keyword: design-for-testability, scan design, generalized feedback/feed-forward shift registers, security, scan-based side-channel attack,
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Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design Hideo FUJIWARA Katsuya FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/08/01 Vol. E99-D No. 8 ; pp. 2182-2185 Type of Manuscript: LETTER Category: Dependable Computing Keyword: design-for-testability, scan design, generalized feedback/feed-forward shift registers, security, scan-based side-channel attack,
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Properties of Generalized Feedback Shift Registers for Secure Scan Design Hideo FUJIWARA Katsuya FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/04/01 Vol. E99-D No. 4 ; pp. 1255-1258 Type of Manuscript: LETTER Category: Dependable Computing Keyword: design-for-testability, scan design, generalized feedback/feed-forward shift registers, security, scan-based side-channel attack,
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Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers Hideo FUJIWARA Katsuya FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2015/10/01 Vol. E98-D No. 10 ; pp. 1852-1855 Type of Manuscript: LETTER Category: Dependable Computing Keyword: design-for-testability, scan design, generalized feed-forward shift registers, security, scan-based side-channel attack,
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Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design Katsuya FUJIWARA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/05/01 Vol. E96-D No. 5 ; pp. 1125-1133 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design-for-testability, scan design, shift register equivalents, shift register quasi-equivalents, generalized feed-forward shift registers, security, scan-based side-channel attack,
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Hybrid Test Application in Partial Skewed-Load Scan Design Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2571-2578 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: delay testing, design-for-testability, skewed-load test application, broad-side test application, partial skewed-load scan design, hybrid test application,
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Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/07/01 Vol. E94-D No. 7 ; pp. 1430-1439 Type of Manuscript: PAPER Category: Dependable Computing Keyword: design-for-testability, scan design, shift register equivalents, security, scan-based side-channel attack,
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Embedded Memory Array Testing Using a Scannable Configuration Seiken YANO Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/25 Vol. E80-A No. 10 ; pp. 1934-1944 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: scannable memory configuration, memory array testing, design-for-testability, scan design,
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Application of Full Scan Design to Embedded Memory Arrays Seiken YANO Katsutoshi AKAGI Hiroki INOHARA Nagisa ISHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/25 Vol. E80-A No. 3 ; pp. 514-520 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: design-for-testability, DFT scan design, scannable memory array, memory array testing,
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