Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/07/25 Vol. E82-DNo. 7 ;
pp. 1126-1130 Type of Manuscript: LETTER Category: Computer Hardware and Design Keyword: design verification, CTL model checker, fair states,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/25 Vol. E76-DNo. 7 ;
pp. 747-754 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: design verification, test program, VHDL, RISC processor,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/10/25 Vol. E75-ANo. 10 ;
pp. 1220-1229 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: design verification, sequential machines, temporal logic, model checking, binary decision diagram,