Keyword : design methodology


Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators
Keisuke OKUNO Toshihiro KONISHI Shintaro IZUMI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1475-1481
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
TDCFSOjitterdesign methodology
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Multistage Function Speculation Adders
Yinan SUN Yongpan LIU Zhibo WANG Huazhong YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/04/01
Vol. E98-A  No. 4 ; pp. 954-965
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multistage function speculationvariable latency adderdesign methodology
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Area-Efficient Microarchitecture for Reinforcement of Turbo Mode
Shinobu MIWA Takara INOUE Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/05/01
Vol. E97-D  No. 5 ; pp. 1196-1210
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
microprocessorsturbo modechip temperaturedesign methodology
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Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3 ; pp. 149-156
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologycircuit descriptionlogic designlayout designdesign verification
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Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout
Tadashi YASUFUKU Yasumi NAKAMURA Zhe PIAO Makoto TAKAMIYA Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1072-1075
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
within-die delay variationdesign methodologylow voltage
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Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 288-295
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologyclock tree synthesisclock skew
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Opposite-Phase Clock Tree for Peak Current Reduction
Yow-Tyng NIEH Shih-Hsu HUANG Sheng-Yu HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2727-2735
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
clocksdesign methodologydigital circuits
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Web Services-Based Security Requirement Elicitation
Carlos GUTIERREZ Eduardo FERNANDEZ-MEDINA Mario PIATTINI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/09/01
Vol. E90-D  No. 9 ; pp. 1374-1387
Type of Manuscript:  PAPER
Category: Software Engineering
Keyword: 
software engineeringdesign methodologysoftware processapplication information security
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Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems
Kwang-Hyun BAEK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 1053-1060
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
high-speed D/A converterdesign methodologyinterconnect modelingbehavioral modelingmixed-mode VLSI
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A Software Radio Receiver with Direct Conversion and Its Digital Processing
Robert MORELOS-ZARAGOZA Shinichiro HARUYAMA Masayoshi ABE Noboru SASHO Lachlan B. MICHAEL Ryuji KOHNO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2002/12/01
Vol. E85-B  No. 12 ; pp. 2741-2749
Type of Manuscript:  Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
software defined radio (SDR)direct conversiondesign methodology
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Acceleration Effect of System Design Process
Alexander M. ZEMLIAK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7 ; pp. 1751-1759
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
design methodologycontrol theory approachacceleration effect
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High-Level Synthesis --A Tutorial
Allen C.-H. WU Youn-Long LIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 209-218
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high-level synthesisdesign methodologyVLSI designdesign automation
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A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories
Masaki TSUKUDA Kazutami ARIMOTO Mikio ASAKURA Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1589-1594
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
reduction of design TATdesign methodologyULSI memory
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PDM: Petri Net Based Development Methodology for Distributed Systems
Mikio AOYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1567-1579
Type of Manuscript:  INVITED PAPER (Special Section on Nets-Oriented Software Specification and Design)
Category: 
Keyword: 
Petri netdistributed systemsconcurrent systemsformal specificationdesign methodologyverification and validationperfomance evaluationand computer-aided software engineering
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A Petri-Net-Based Programming Environment and Its Design Methodology for Cooperating Discrete Event Systems
Naoshi UCHIHIRA Mikako ARAMI Shinichi HONIDEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1335-1347
Type of Manuscript:  Special Section PAPER (Special Section on Application of Petri Nets to Concurrent System Design)
Category: 
Keyword: 
high level petri netcooperating discrete event systemconcurrent programdesign methodologyprogram synthesisprogram verificationtemporal logicprogramming environment
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