Keyword : design for testability


A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
Widiant Masaki HASHIZUME Shohei SUENAGA Hiroyuki YOTSUYANAGI Akira ONO Shyue-Kung LU Zvi ROTH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/11/01
Vol. E99-D  No. 11 ; pp. 2723-2733
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
electrical testbuilt-in test circuitopen defectinterconnect testdesign for testability
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Complex Networks Clustering for Lower Power Scan Segmentation in At-Speed Testing
Zhou JIANG Guiming LUO Kele SHEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/09/01
Vol. E99-C  No. 9 ; pp. 1071-1079
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
scan testscan segmentationlower power testingcomplex networks clusteringdesign for testabilityat-speed testing
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On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Hiroyuki YOTSUYANAGI Hiroyuki MAKIMOTO Takanobu NIMIYA Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
delay testingtime-to-digital converterboundary scandesign for testability
 Summary | Full Text:PDF

A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines
Kiichi NIITSU Naohiro HARIGAI Takahiro J. YAMAGUCHI Haruo KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6 ; pp. 920-922
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
time amplifierfeed-forwardCMOSintegrated circuitsdesign for testability
 Summary | Full Text:PDF

A C-Testable Multiple-Block Carry Select Adder
Nobutaka KITO Shinichi FUJII Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4 ; pp. 1084-1092
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
carry select adderdesign for testabilityC-testability
 Summary | Full Text:PDF

An Easily Testable Routing Architecture and Prototype Chip
Kazuki INOUE Masahiro KOGA Motoki AMAGASAKI Masahiro IIDA Yoshinobu ICHIDA Mitsuro SAJI Jun IIDA Toshinori SUEYOSHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 303-313
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
design for testabilityhomogeneous architecturetest methodprototype chip
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Design for Testability That Reduces Linearity Testing Time of SAR ADCs
Tomohiko OGAWA Haruo KOBAYASHI Satoshi UEMORI Yohei TAN Satoshi ITO Nobukazu TAKAI Takahiro J. YAMAGUCHI Kiichi NIITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1061-1064
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
SAR ADCtestingDC linearitydesign for testabilitybuilt-in self-test
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A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
Nobutaka KITO Kensuke HANAI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10 ; pp. 2783-2791
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
multiplierdesign for testability4-2 adder treeC-testability
 Summary | Full Text:PDF

Design and Optimization of Transparency-Based TAM for SoC Test
Tomokazu YONEDA Akiko SHUTO Hideyuki ICHIHARA Tomoo INOUE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Vol. E93-D  No. 6 ; pp. 1549-1559
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
SoC testdesign for testabilityTAM designtransparencyILP
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Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method
Youbean KIM Jaewon JANG Hyunwook SON Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/03/01
Vol. E93-D  No. 3 ; pp. 643-646
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
BISTlow power BISTdesign for testability
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Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2 ; pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
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Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
Masato NAKAZATO Michiko INOUE Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 763-770
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: High-Level Testing
Keyword: 
software-based self-testprocessortest program templatedesign for testabilityerror maskingat-speed testing
 Summary | Full Text:PDF

Low-Cost IP Core Test Using Tri-Template-Based Codes
Gang ZENG Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/01/01
Vol. E90-D  No. 1 ; pp. 288-295
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityIP core testingtest cost reductiontest data compression
 Summary | Full Text:PDF

Proposal of Testable Multi-Context FPGA Architecture
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/05/01
Vol. E89-D  No. 5 ; pp. 1687-1693
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
multi-context FPGAsingle stuck-at faultdesign for testability
 Summary | Full Text:PDF

Classification of Sequential Circuits Based on τk Notation and Its Applications
Chia Yee OOI Thomas CLOUQUEUR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2738-2747
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
test generationeasily testable sequential circuitscomplexitydesign for testabilitysynthesis for testability
 Summary | Full Text:PDF

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths
Zhiqiang YOU Ken'ichi YAMAGUCHI Michiko INOUE Jacob SAVIR Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/08/01
Vol. E88-D  No. 8 ; pp. 1940-1947
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design for testabilityRTL data pathbuilt-in self-testlow power testingtest scheduling
 Summary | Full Text:PDF

Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns
James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 1024-1030
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
diagnosisdesign for testabilitydelay fault testing
 Summary | Full Text:PDF

Design for Two-Pattern Testability of Controller-Data Path Circuits
Md. ALTAF-UL-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/06/01
Vol. E86-D  No. 6 ; pp. 1042-1050
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilityhierarchical testabilitydelay testingcontroller-data path circuittwo-pattern testability
 Summary | Full Text:PDF

Design for Hierarchical Two-Pattern Testability of Data Paths
Md. Altaf-Ul-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/06/01
Vol. E85-D  No. 6 ; pp. 975-984
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilitydelay testinghierarchical testabilitytwo-pattern testability
 Summary | Full Text:PDF

A VLSI Scan-Chain Optimization Algorithm for Multiple Scan-Paths
Susumu KOBAYASHI Masato EDAHIRO Mikio KUBO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2499-2504
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSI CADscan-chainlayout designdesign for testability
 Summary | Full Text:PDF

Register-Transfer Level Testability Analysis and Its Application to Design for Testability
Mizuki TAKAHASHI Ryoji SAKURAI Hiroaki NODA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2646-2654
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
testability analysisregister transfer leveldesign for testability
 Summary | Full Text:PDF

Improving Random Pattern Testability with Partial Circuit Duplication Approach
Hiroshi YOKOYAMA Xiaoqing WEN Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 654-659
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
partial circuit duplicationrandom testingdesign for testabilitybuilt-in self-test
 Summary | Full Text:PDF

Partial Scan Design Methods Based on n-Fold Line-Up Structures and the State Justification of Pure Load/Hold Flip-Flops
Toshinori HOSOKAWA Toshihiro HIRAOKA Mitsuyasu OHTA Michiaki MURAOKA Shigeo KUNINOBU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 660-667
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan design methodn-fold line-up structurepure load/hold FF
 Summary | Full Text:PDF

A Partial Scan Design Approach based on Register-Transfer Level Testability Analysis
Akira MOTOHARA Sadami TAKEOKA Mitsuyasu OHTA Michiaki MURAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1436-1442
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Design for Testability
Keyword: 
design for testabilitypartial scan designregister-transfer levelautomatic test-pattern generationESDA
 Summary | Full Text:PDF

A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs
Yukiya MIURA Sachio NAITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 845-852
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
current testing (IDDQ testing)built-in testdesign for testabilitydigital and mixed-signal circuit testing
 Summary | Full Text:PDF

The Effect of CMOS VLSI IDDq Measurement on Defect Level
Junichi HIRASE Masanori HAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 839-844
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
IDDq testCMOS VLSIfault coveragedefect leveltoggle ratestuck-at faultdesign for testability
 Summary | Full Text:PDF

A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuittest generationdesign for testabilityscan circuitreduced scan shift
 Summary | Full Text:PDF

Design of Repairable Cellular Arrays on Multiple-Valued Logic
Naotake KAMIURA Yutaka HATA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/08/25
Vol. E77-D  No. 8 ; pp. 877-884
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple-valued logicecllular arrayfault diagnosisrepairdesign for testability
 Summary | Full Text:PDF

Synthesis of Testable Sequential Circuits with Reduced Checking Sequences
Satoshi SHIBATANI Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 739-746
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
sequential circuitdesign for testabilityautomated logic synthesischecking sequencestate assignment
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A Testable Design of Sequential Circuits under Highly Observable Condition
WEN Xiaoqing Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3 ; pp. 334-341
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
design for testabilityhighly observable testingfault diagnosissequential circuitcircuit modification
 Summary | Full Text:PDF