Keyword : design for testability (DfT)


Built-In Measurements in Low-Cost Digital-RF Transceivers
Oren ELIEZER Robert Bogdan STASZEWSKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 930-937
Type of Manuscript:  INVITED PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
system-on-chip (SoC)digital RF processor (DRP)design for testability (DfT)design for manufacturability (DfM)built-in self-testing (BiST)soft specifications
 Summary | Full Text:PDF

Selective Scan Slice Grouping Technique for Efficient Test Data Compression
Yongjoon KIM Jaeseok PARK Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/02/01
Vol. E93-D  No. 2 ; pp. 380-383
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design for testability (DfT)scan testingSoC testtest data compression
 Summary | Full Text:PDF

A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption
Yongjoon KIM Jaeseok PARK Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/01/01
Vol. E93-D  No. 1 ; pp. 193-196
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design for testability (DfT)scan testingscan cell reorderinglow power test
 Summary | Full Text:PDF

Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time
Yongjoon KIM Myung-Hoon YANG Jaeseok PARK Eunsei PARK Sungho KANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/07/01
Vol. E92-D  No. 7 ; pp. 1462-1465
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
design for testability (DfT)scan testingtest data compression
 Summary | Full Text:PDF