Keyword : design for testability (DFT)


A Low-Cost Stimulus Design for Linearity Test in SAR ADCs
An-Sheng CHAO Cheng-Wu LIN Hsin-Wen TING Soon-Jyh CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/06/01
Vol. E97-C  No. 6 ; pp. 538-545
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
analog-to-digital converter (ADC)design for testability (DFT)pattern generator (PG)output response analyzer (ORA)
 Summary | Full Text:PDF(2.1MB)

Design of C-Testable Modified-Booth Multipliers
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/10/25
Vol. E83-D  No. 10 ; pp. 1868-1878
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
multipliermodified Booth Algorithmdesign for testability (DFT)C-testable design
 Summary | Full Text:PDF(873.5KB)