Keyword : design for test


A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips
Masahide MIYAZAKI Tomokazu YONEDA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1490-1497
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
SoCtest schedulingwrapperdesign for testmemory BIST
 Summary | Full Text:PDF(1MB)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips
Masahide MIYAZAKI Toshinori HOSOKAWA Hiroshi DATE Michiaki MURAOKA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 609-619
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: SoC Testing
Keyword: 
test schedulingtest access mechanismwrapperdesign for test
 Summary | Full Text:PDF(2.2MB)