IEICE Trans

Keyword : delay-locked loop

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines Nobutaro SHIBATA Mitsuo NAKAMURA
Publication: Publication Date: 2018/08/01 Vol. E101-A No. 8 ; pp. 1185-1196 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: ATE, delay-locked loop, digital-to-time converter, linearity error, on the fly, plain CMOS logic, timing jitter, timing vernier,
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Design of a Compact Double-Channel 5-Gb/s/ch Serializer Array for High-Speed Parallel Links Chang-chun ZHANG Long MIAO Kui-ying YIN Yu-feng GUO Lei-lei LIU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/11/01 Vol. E97-C No. 11 ; pp. 1104-1111 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: CMOS, serializer, phase-locked loop, delay-locked loop, parallel links,
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Performance of DS/SS System Using Pseudo-Ternary M-Sequences Ryo ENOMOTO Hiromasa HABUCHI Koichiro HASHIURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/11/01 Vol. E93-A No. 11 ; pp. 2299-2306 Type of Manuscript: Special Section PAPER (Special Section on Signal Design and its Application in Communications) Category: Spread Spectrum Technologies and Applications Keyword: spreading code sequence, spread spectrum, signal tracking, delay-locked loop, jitter, bit error rate,
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A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop Hsin-Shu CHEN Jyun-Cheng LIN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 ; pp. 855-860 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: delay-locked loop, fast-lock, low-power, subranging,
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A Multiphase Generator Based on VCDR (Voltage-Controlled Variable Delay Ring) Minseok WOO Byoungkwon MOON Daejeong KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/10/01 Vol. E92-C No. 10 ; pp. 1315-1318 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: delay-locked loop, phase multiplication,
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Deadzone-Minimized Systematic Offset-Free Phase Detectors Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 ; pp. 1525-1528 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: phase detector, phase offset, deadzone, multiphase generation, delay-locked loop, phase-locked loop,
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A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology Ching-Yuan YANG Chih-Hsiang CHANG Wen-Ger WONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 ; pp. 497-503 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: spread spectrum clock generation, fractional phase-locked loop, delay-locked loop, phase compensation, fractional divider,
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A Wide Frequency Range Delay-Locked Loop Using Multi-Phase Frequency Detection Technique Kang-Yoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/09/01 Vol. E88-C No. 9 ; pp. 1900-1902 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: delay-locked loop, multi-phase, frequency detection, jitter,
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A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM Band Seok KANG Beomsup KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/01/01 Vol. E88-C No. 1 ; pp. 149-153 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: frequency synthesis, delay-locked loop, edge combine,
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A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges Koichiro MINAMI Masayuki MIZUNO Hiroshi YAMAGUCHI Toshihiko NAKANO Yusuke MATSUSHIMA Yoshikazu SUMI Takanori SATO Hisashi YAMASHIDA Masakazu YAMASHINA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 ; pp. 220-228 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: delay-locked loop, infinite phase capture ranges, variable delay line, dynamic phase detector,
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Coherent Delay-Locked Code Tracking Loop Using Time-Multiplexed Pilot for DS-CDMA Mobile Radio Mamoru SAWAHASHI Fumiyuki ADACHI Heiichi YAMAMOTO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/07/25 Vol. E81-B No. 7 ; pp. 1426-1432 Type of Manuscript: Special Section PAPER (Special Issue on Third Generation Land Mobile Communication Systems) Category: Keyword: delay-locked loop, DS-CDMA, mobile radio,
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