Keyword : delay variation


Discrimination of a Resistive Open Using Anomaly Detection of Delay Variation Induced by Transitions on Adjacent Lines
Hiroyuki YOTSUYANAGI Kotaro ISE Masaki HASHIZUME Yoshinobu HIGAMI Hiroshi TAKAHASHI 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2842-2850
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
resistive opensmall delay faultadjacent linedelay variationanomaly detection
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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation
Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1439-1451
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesisdelay variationbody biasinginterconnection delayfloorplan
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An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead
Shinnosuke YOSHIDA Youhua SHI Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1406-1418
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
timing-error predictionrobust designdelay variationoverclocking
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A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement
Hayato MASHIKO Yukihide KOHIRA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2443-2450
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay variationtiming violationyieldprogrammable delay element
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Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/04/01
Vol. E94-A  No. 4 ; pp. 1067-1081
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapath synthesisdelay variationregister assignmenthold timing constraintbackward-data-direction clockinginteger linear programming
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Impact of Self-Heating in Wire Interconnection on Timing
Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 388-392
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectdelay variationparasitic resistancethermaltemperatureself-heatSoC
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Scalable Parallel Interface for Terabit LAN
Shoukei KOBAYASHI Yoshiaki YAMADA Kenji HISADOME Osamu KAMATANI Osamu ISHIDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2009/10/01
Vol. E92-B  No. 10 ; pp. 3015-3021
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Information and Communication Technologies and Services in Conjunction with Main Topics of APCC/COIN 2008)
Category: 
Keyword: 
Terabit LANLambda Accesspacket-based lane bundlingaggregated bandwidth linklink aggregationinverse multiplexingtime informationdelay variationdelay controllability
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On Window Control Algorithm over Wireless Cellular Networks with Large Delay Variation
Ho-Jin LEE Hee-Jung BYUN Jong-Tae LIM 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2009/06/01
Vol. E92-B  No. 6 ; pp. 2279-2282
Type of Manuscript:  LETTER
Category: Network
Keyword: 
congestion avoidancewireless cellular networksdelay variation
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Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1096-1105
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesisdelay variationregister assignmentsetup and hold constraintsminimum delay compensationinteger linear programming
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Way-Scaling to Reduce Power of Cache with Delay Variation
Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3576-3584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
leakagepower reductioncachewithin-die variationdelay variationway scaling
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Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
Keisuke INOUE Mineo KANEKO Tsuyoshi IWAGAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1044-1053
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
datapath synthesisdelay variationregister assignmentsetup and hold constraints
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Performance Monitoring of VoIP Flows for Large Network Operations
Yoshinori KITATSUJI Satoshi KATSUNO Katsuyuki YAMAZAKI Masato TSURU Yuji OIE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/10/01
Vol. E90-B  No. 10 ; pp. 2746-2754
Type of Manuscript:  Special Section PAPER (Special Section on New Challenge for Internet Technology and its Architecture)
Category: 
Keyword: 
performance monitoringVoIPIP flowdelay variationand inter-packet gap
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Design Method of High Performance and Low Power Functional Units Considering Delay Variations
Kouichi WATANABE Masashi IMAI Masaaki KONDO Hiroshi NAKAMURA Takashi NANYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3519-3528
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
delay variationdual-rail asynchronous circuitfunctional unitunflip-bit control
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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3666-3670
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
interconnectdelay variationparasitic capacitanceSoC
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Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise
Mitsuya FUKAZAWA Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1559-1566
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
delay variationdynamic power supply noisestatic IR dropon-chip waveform monitor circuitsignal integrity
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On Efficient Core Selection for Reducing Multicast Delay Variation under Delay Constraints
Moonseong KIM Young-Cheol BANG Hyung-Jin LIM Hyunseung CHOO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/09/01
Vol. E89-B  No. 9 ; pp. 2385-2393
Type of Manuscript:  Special Section PAPER (Special Section on Networking Technologies for Overlay Networks)
Category: 
Keyword: 
multicast routingdelay variationdelay- and delay variation-bounded multicast tree (DVBMT) problem
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An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity
Koichiro NOGUCHI Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 761-768
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
signal integritysubstrate crosstalkdelay variationon-chip monitor
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Hardware-Based Precise Time Synchronization on Gb/s Ethernet Enhanced with Preemptive Priority
Yoshiaki YAMADA Satoru OHTA Hitoshi UEMATSU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/03/01
Vol. E89-B  No. 3 ; pp. 683-689
Type of Manuscript:  Special Section PAPER (Special Section on the Next Generation Ethernet Technologies)
Category: 
Keyword: 
Ethernetsynchronizationdelay variationpriorityQoS
 Summary | Full Text:PDF