Keyword : delay testing


On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan
Hiroyuki YOTSUYANAGI Hiroyuki MAKIMOTO Takanobu NIMIYA Masaki HASHIZUME 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1986-1993
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
delay testingtime-to-digital converterboundary scandesign for testability
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A Delay Evaluation Circuit for Analog BIST Function
Zhengliang LV Shiyuan YANG Hong WANG Linda MILOR 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/03/01
Vol. E96-C  No. 3 ; pp. 393-401
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
delay testingBISTanalog filtersample-hold circuit
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Hybrid Test Application in Partial Skewed-Load Scan Design
Yuki YOSHIKAWA Tomomi NUWA Hideyuki ICHIHARA Tomoo INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2571-2578
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
delay testingdesign-for-testabilityskewed-load test applicationbroad-side test applicationpartial skewed-load scan designhybrid test application
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A Statistical Quality Model for Delay Testing
Yasuo SATO Shuji HAMADA Toshiyuki MAEDA Atsuo TAKATORI Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 349-355
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Signal Integrity and Variability
Keyword: 
delay testingquality modeldefect distribution
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Evaluation of Delay Testing Based on Path Selection
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA Shinichi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3208-3210
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
delay testingpath delay faultpath selectionuntestable path
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Design for Two-Pattern Testability of Controller-Data Path Circuits
Md. ALTAF-UL-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/06/01
Vol. E86-D  No. 6 ; pp. 1042-1050
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilityhierarchical testabilitydelay testingcontroller-data path circuittwo-pattern testability
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High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword: 
delay testingpath selectionfault simulationtest generationpath-status graph
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Design for Hierarchical Two-Pattern Testability of Data Paths
Md. Altaf-Ul-AMIN Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/06/01
Vol. E85-D  No. 6 ; pp. 975-984
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
design for testabilitydelay testinghierarchical testabilitytwo-pattern testability
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