Keyword : delay model


A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal Operations
Noboru TAKAGI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2040-2047
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Logic Design
Keyword: 
multiple-valued logicmultiple-valued logic circuitshazard detectiondelay model
 Summary | Full Text:PDF(170KB)

The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure
Sang Heon LEE Song Bai PARK Kyu Ho PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/01/25
Vol. E78-A  No. 1 ; pp. 142-145
Type of Manuscript:  LETTER
Category: VLSI Design Technology
Keyword: 
computer aided design (CAD)modeling and simulationparasitic capacitancedelay modelseries-connected MOS structure
 Summary | Full Text:PDF(258.7KB)

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
Ikuo HARADA Yuichiro TAKEI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2058-2066
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routingtiming driven layoutbipolar LSIdelay modelrouting graphcritical path
 Summary | Full Text:PDF(893.5KB)