Keyword : delay insertion

Delay Insertion Based P2PTV Traffic Localization Considering Peer's Relaying Capability
Chitapong WECHTAISONG Hiroaki MORINO 
Publication:   
Publication Date: 2017/10/01
Vol. E100-B  No. 10 ; pp. 1798-1806
Type of Manuscript:  PAPER
Category: Network
Keyword: 
P2PTV, traffic localization, relay capability estimation, delay insertion, 
 Summary | Full Text:PDF
A Router-Aided Hierarchical P2P Traffic Localization Based on Variable Additional Delay Insertion
Hiep HOANG-VAN Yuki SHINOZAKI Takumi MIYOSHI Olivier FOURMAUX 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2014/01/01
Vol. E97-B  No. 1 ; pp. 29-39
Type of Manuscript:  Special Section PAPER (Special Section on Management for Flexible ICT Systems and Services)
Category: 
Keyword: 
P2P, router-aided approach, hierarchical traffic localization, delay insertion, 
 Summary | Full Text:PDF
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework
Yukihide KOHIRA Shuhei TANI Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1106-1114
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
delay insertion, clock scheduling, general-synchronous framework, 
 Summary | Full Text:PDF
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion
Yukihide KOHIRA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 892-898
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
delay insertion, clock period minimization, semi-synchronous circuit, delay-slack, delay-demand, 
 Summary | Full Text:PDF
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
Tomoyuki YODA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2383-2389
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
delay insertion, clock period minimization, semi-synchronous circuit, 
 Summary | Full Text:PDF