Keyword : delay fault


Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment
Yoshinobu HIGAMI Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/06/01
Vol. E96-D  No. 6 ; pp. 1323-1331
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test generationfault simulationclock linedelay fault
 Summary | Full Text:PDF(595KB)

A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3200-3207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
controllerdelay faultnon-scan designinvalid test state and transition generatorat-speed test
 Summary | Full Text:PDF(463.8KB)

Delay Fault Testing for CMOS Iterative Logic Arrays with a Constant Number of Patterns
Shyue-Kung LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2659-2665
Type of Manuscript:  Special Section PAPER (Special Issue on Dependable Computing)
Category: Test
Keyword: 
delay faultIterative Logic ArrayC-testablebijection
 Summary | Full Text:PDF(742KB)