Keyword : delay fault testing


Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing
Masahiro ISHIDA Toru NAKURA Takashi KUSAKA Satoshi KOMATSU Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/10/01
Vol. E99-C  No. 10 ; pp. 1219-1225
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
power integritypower supply voltage controloverkills and underkillsdelay fault testingautomatic test equipment
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Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/03/01
Vol. E92-D  No. 3 ; pp. 433-442
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
dual circuitsmaster and slave scan pathsdelay fault testingconcurrent error detectionDFT
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Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2 ; pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
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Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2 ; pp. 269-282
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
test compressionstatistical codingrun-length codingdelay fault testingtwo-pattern testingscan testing
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Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingdelay fault testingscan designenhanced scan
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Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns
James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 1024-1030
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
diagnosisdesign for testabilitydelay fault testing
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Delay Fault Testing of Processor Cores in Functional Mode
Virendra SINGH Michiko INOUE Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/03/01
Vol. E88-D  No. 3 ; pp. 610-618
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
processor testdelay fault testingsoftware-based self-testat-speed test
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A Design for Testability Technique for Low Power Delay Fault Testing
James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 621-628
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
testability technology (design for testability)delay fault testinglow powerASIC
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