IEICE SEARCH SYSTEM

Keyword : decoder

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications Mungyu KIM Hoon-Ju CHUNG Young-Chan JANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 ; pp. 519-525 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: digital-to-analog converter, resistor string, logarithmic time interpolator, low-pass filter, decoder,
	Summary \| Full Text:PDF(1.6MB)

High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems Chang-Seok CHOI Hyo-Jin AHN Hanho LEE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2011/05/01 Vol. E94-B No. 5 ; pp. 1332-1338 Type of Manuscript: PAPER Category: Network Keyword: forward error correction (FEC), Reed-Solomon (RS), decoder, mmWAVE, WPAN,
	Summary \| Full Text:PDF(1.3MB)

An Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm Jui-Hui HUNG Sau-Gee CHEN
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/11/01 Vol. E93-B No. 11 ; pp. 2980-2989 Type of Manuscript: PAPER Category: Fundamental Theories for Communications Keyword: channel coding, LDPC, decoder, algorithm, hardware,
	Summary \| Full Text:PDF(1008.4KB)

Low-Complexity Semi-Coherent MIMO Systems Mohd Hairi HALMI Mohamad Yusoff ALIAS Teong Chee CHUAH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/04/01 Vol. E93-A No. 4 ; pp. 833-836 Type of Manuscript: LETTER Category: Digital Signal Processing Keyword: MIMO, STBC, semi-coherent, detector, decoder,
	Summary \| Full Text:PDF(254.1KB)

A High Performance Serially Mixed SOVA Decoder for Turbo Code Sang-Sic YOON Hyung-Chul PARK Kwyro LEE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2002/01/01 Vol. E85-B No. 1 ; pp. 332-335 Type of Manuscript: LETTER Category: Fundamental Theories Keyword: turbo, SOVA, decoder, backward, bidirectional,
	Summary \| Full Text:PDF(673KB)

Parallel Encoder and Decoder Architecture for Cyclic Codes Tomoko K. MATSUSHIMA Toshiyasu MATSUSHIMA Shigeichi HIRASAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/09/25 Vol. E79-A No. 9 ; pp. 1313-1323 Type of Manuscript: Special Section PAPER (Special Section on Information Theory and Its Applications) Category: Coding Theory Keyword: error correction, cyclic code, parallel architecture, circuit design, encoder, decoder,
	Summary \| Full Text:PDF(772.7KB)

High-Performance Memory Macrocells with Row and Column Sliceable Architecture Nobutaro SHIBATA Yoshinori GOTOH Shigeru DATE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/11/25 Vol. E76-C No. 11 ; pp. 1641-1648 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memories) Category: Application Specific Memory Keyword: ASIC, CMOS, macrocell, memory, configurable, row sliceable, decoder, short design Turn-Around-Time (TAT),
	Summary \| Full Text:PDF(692.2KB)

Four-Valued Dynamic Encoder and Decoder Circuits for CMOS Multivalued Logic Systems Kazutaka TANIGUCHI Fumio UENO Takahiro INOUE Toshitsugu YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/25 Vol. E75-C No. 10 ; pp. 1275-1280 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: multivalued logic, encoder, decoder,
	Summary \| Full Text:PDF(427.9KB)